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MC100EP16VBDTR2 PDF预览

MC100EP16VBDTR2

更新时间： 2024-09-29 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
10页 151K
描述
3.3V / 5V ECL Differential Receiver/Driver with High and Low Gain

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中文翻译

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MC100EP16VBDTR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：PLASTIC, TSSOP-8
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.48其他特性：CAN ALSO OPERATE WITH -3V TO -5.5V SUPPLY IN NECL MODE
差分输出：YES驱动器位数：1
高电平输入电流最大值：0.00015 A输入特性：DIFFERENTIAL
接口集成电路类型：LINE TRANSCEIVER接口标准：GENERAL PURPOSE
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：3 mm标称负供电电压：-4.5 V
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.19封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：-4.5 V认证状态：Not Qualified
最大接收延迟：0.4 ns接收器位数：1
座面最大高度：1.1 mm子类别：Line Driver or Receivers
最大压摆率：38 mA最大供电电压：5.5 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn90Pb10)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
最大传输延迟：0.4 ns宽度：3 mm
Base Number Matches：1

MC100EP16VBDTR2 数据手册

 浏览型号MC100EP16VBDTR2的Datasheet PDF文件第2页浏览型号MC100EP16VBDTR2的Datasheet PDF文件第3页浏览型号MC100EP16VBDTR2的Datasheet PDF文件第4页浏览型号MC100EP16VBDTR2的Datasheet PDF文件第5页浏览型号MC100EP16VBDTR2的Datasheet PDF文件第6页浏览型号MC100EP16VBDTR2的Datasheet PDF文件第7页 
MC100EP16VB  
3.3Vꢀ/ꢀ5VꢁECL Differential  
Receiver/Driver with High  
and Low Gain  
Description  
http://onsemi.com  
MARKING DIAGRAMS*  
The EP16VB is a world−class differential receiver/driver. The  
device is functionally equivalent to the EP16 and LVEP16 devices but  
with both high and low gain outputs. Q and Q outputs have a DC  
HG  
HG  
gain several times larger than the DC gain of an EP16. Q output is  
provided for feedback purposes.  
8
KEP65  
ALYW  
G
SOIC−8  
D SUFFIX  
CASE 751  
The V pin, an internally generated voltage supply, is available to  
BB  
8
this device only. For single-ended input conditions, the unused  
1
1
differential input is connected to V as a switching reference voltage.  
1
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
8
1
to 0.5 mA. When not used, V should be left open.  
BB  
TSSOP−8  
DT SUFFIX  
CASE 948R  
KP65  
8
Special considerations are required for differential inputs under No  
Signal conditions to prevent instability.  
The 100 Series contains temperature compensation.  
ALYWG  
G
Features  
• Gain > 200  
• Maximum Frequency > 3 GHz Typical  
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
A
L
Y
W
M
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Date Code  
= Pb−Free Package  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
• V Output  
BB  
• Pb−Free Packages are Available  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 4  
MC100EP16VB/D  
1234567...10

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MC100EP16VBDTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP16VBDTR2G ONSEMI

完全替代

 3.3V / 5V ECL Differential Receiver/Driver with High and Low Gain
MC100EP16VBDTG ONSEMI

完全替代

 3.3V / 5V ECL Differential Receiver/Driver with High and Low Gain
MC100EP16VBDT ONSEMI

类似代替

 3.3V / 5V ECL Differential Receiver/Driver with High and Low Gain

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