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MC100EP016A

更新时间： 2024-11-26 23:01:31

品牌	Logo	应用领域
安森美 - ONSEMI		计数器
页数	文件大小	规格书
12页	102K
描述
3.3 V ECL 8-Bit Synchronous Binary Up Counter

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MC100EP016A 数据手册

MC100EP016A

3.3 VꢀECL 8−Bit

Synchronous Binary

Up Counter

The MC100EP016A is a high−speed synchronous, presettable,

cascadeable 8−bit binary counter. Architecture and operation are the

same as the ECLinPS family MC100E016 with higher operating

speed.

http://onsemi.com

MARKING

The counter features internal feedback to TC gated by the TCLD

(Terminal Count Load) pin. When TCLD is LOW (or left open, in

which case it is pulled LOW by the internal pulldowns), the TC

feedback is disabled, and counting proceeds continuously, with TC

going LOW to indicate an all−one state. When TCLD is HIGH, the TC

feedback causes the counter to automatically reload upon TC = LOW,

thus functioning as a programmable counter. The Qn outputs do not

need to be terminated for the count function to operate properly. To

minimize noise and power, unused Q outputs should be left

unterminated.

DIAGRAM*

LQFP−32

FA SUFFIX

CASE 873A

MC100

EP016A

AWLYYWW

COUT and COUT provide differential outputs from a single,

non−cascaded counter or divider application. COUT and COUT

should not be used in cascade configuration. Only TC should be used

for a counter or divider cascade chain output.

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

A differential clock input has also been added to improve

performance.

The 100 Series contains temperature compensation.

*For additional information, see Application Note

AND8002/D

• 550 ps Typical Propagation Delay

• Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016

ORDERING INFORMATION

• PECL Mode Operating Range: V = 3.0 V to 3.6 V

†

with V = 0 V

Device

Package

Shipping

• NECL Mode Operating Range: V = 0 V

MC100EP016AFA

LQFP−32

250 Units/Tray

with V = −3.0 V to −3.6 V

MC100EP016AFAR2 LQFP−32 2000/Tape & Reel

• Open Input Default State

• Safety Clamp on Clock Inputs

• Internal TC Feedback (Gated)

• Addition of COUT and COUT

• 8−Bit

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• Differential Clock Input

• V Output

• Fully Synchronous Counting and TC Generation

• Asynchronous Master Reset

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

May 2004 − Rev. 4

MC100EP016A/D

12 3 4 5 6 7...12

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与MC100EP016A相关器件

型号	品牌	获取价格	描述	数据表
MC100EP016A_06	ONSEMI	获取价格	3.3 V ECL 8−Bit Synchronous Binary Up Counter
MC100EP016AFA	ONSEMI	获取价格	3.3 V ECL 8-Bit Synchronous Binary Up Counter
MC100EP016AFAG	ONSEMI	获取价格	3.3 V ECL 8−Bit Synchronous Binary Up Counter
MC100EP016AFAR2	ONSEMI	获取价格	3.3 V ECL 8-Bit Synchronous Binary Up Counter
MC100EP016AFAR2G	ONSEMI	获取价格	3.3 V ECL 8−Bit Synchronous Binary Up Counter
MC100EP016AMNG	ONSEMI	获取价格	3.3 V ECL 8-Bit Synchronous Binary Up Counter
MC100EP016AMNR2G	ONSEMI	获取价格	100E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, QCC32, 5 X 5 MM, 1 MM HE
MC100EP016AMNR4G	ONSEMI	获取价格	ECL 8 位同步二进制计数器
MC100EP016FA	ONSEMI	获取价格	3.3V / 5VECL 8-Bit Synchronous Binary Up Counter
MC100EP016FA	CHERRY	获取价格	Binary Counter, PQFP32, PLASTIC, TQFP-32

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