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MC-4532DA726EFB-A80 PDF预览

MC-4532DA726EFB-A80

更新时间： 2024-11-24 22:20:27
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路动态存储器
页数 文件大小 规格书
16页 248K
描述
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

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中文翻译

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MC-4532DA726EFB-A80 技术参数

生命周期：Transferred零件包装代码：DIMM
包装说明：,针数：168
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.36风险等级：5.6
Is Samacsys：N访问模式：FOUR BANK PAGE BURST
最长访问时间：6 nsJESD-30 代码：R-XDMA-N168
内存密度：2415919104 bit内存集成电路类型：SYNCHRONOUS DRAM MODULE
内存宽度：72功能数量：1
端口数量：1端子数量：168
字数：33554432 words字数代码：32000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32MX72
封装主体材料：UNSPECIFIED封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY认证状态：Not Qualified
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：MOS温度等级：COMMERCIAL
端子形式：NO LEAD端子位置：DUAL
Base Number Matches：1

MC-4532DA726EFB-A80 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-4532DA726  
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
REGISTERED TYPE  
Description  
The MC-4532DA726 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of  
128M SDRAM: µPD45128441 are assembled.  
These modules provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
• 33,554,432 words by 72 bits organization (ECC type)  
• Clock frequency and access time from CLK  
Part number  
/CAS latency  
Clock frequency  
(MAX.)  
Access time from CLK  
(MAX.)  
Module type  
MC-4532DA726EFB-A80  
MC-4532DA726EFB-A10  
MC-4532DA726PFB-A80  
MC-4532DA726PFB-A10  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
6 ns  
6 ns  
6 ns  
7 ns  
6 ns  
6 ns  
6 ns  
7 ns  
PC100 Registered DIMM  
Rev. 1.2 Compliant  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
★
★
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
• Pulsed interface  
• Possible to assert random column address in every cycle  
• Quad internal banks controlled by BA0 and BA1 (Bank Select)  
• Programmable burst-length (1, 2, 4, 8 and Full Page)  
• Programmable wrap sequence (Sequential / Interleave)  
• Programmable /CAS latency (2, 3)  
• Automatic precharge and controlled precharge  
• CBR (Auto) refresh and self refresh  
• All DQs have 10 Ω ± 10 % of series resistor  
• Single 3.3 V ± 0.3 V power supply  
• LVTTL compatible  
• 4,096 refresh cycles / 64 ms  
• Burst termination by Burst Stop command and Precharge command  
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)  
• Registered type  
• Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. M13633EJ7V0DS00 (7th edition)  
Date Published February 2000 NS CP(K)  
Printed in Japan  
The mark ★ shows major revised points.  
1998  
©
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 		32M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

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