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MC-4532CD647XF-A75 PDF预览

MC-4532CD647XF-A75

更新时间: 2024-11-25 11:11:15
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
16页 161K
描述
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

MC-4532CD647XF-A75 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM168
针数:168Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.83Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:2147483648 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:168
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.016 A子类别:DRAMs
最大压摆率:2.16 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MC-4532CD647XF-A75 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-4532CD647  
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
UNBUFFERED TYPE  
Description  
The MC-4532CD647EF, MC-4532CD647PF and MC-4532CD647XF are 33,554,432 words by 64 bits synchronous  
dynamic RAM module on which 16 pieces of 128M SDRAM: µPD45128841 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
33,554,432 words by 64 bits organization  
Clock frequency and access time from CLK.  
Part number  
/CAS latency  
Clock frequency  
(MAX.)  
Access time from CLK  
(MAX.)  
MC-4532CD647EF-A75  
MC-4532CD647PF-A75  
MC-4532CD647XF-A75  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
133 MHz  
100 MHz  
133 MHz  
100 MHz  
133 MHz  
100 MHz  
5.4 ns  
6.0 ns  
5.4 ns  
6.0 ns  
5.4 ns  
6.0 ns  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0 and BA1 (Bank Select)  
Programmable burst-length (1, 2, 4, 8 and full page)  
Programmable wrap sequence (Sequential / Interleave)  
Programmable /CAS latency (2, 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
All DQs have 10 Ω ±10 % of series resistor  
Single 3.3 V ± 0.3 V power supply  
LVTTL compatible  
4,096 refresh cycles/64 ms  
Burst termination by Burst Stop command and Precharge command  
168-pin dual in-line memory module (Pin pitch = 1.27 mm)  
Unbuffered type  
Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0054N20 (Ver. 2.0)  
Date Published March 2001 CP (K)  
Printed in Japan  
This product became EOL in September, 2002.  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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