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MBM29LV400BC-70PBT PDF预览

MBM29LV400BC-70PBT

更新时间: 2024-11-04 23:05:43
品牌 Logo 应用领域
富士通 - FUJITSU 闪存存储内存集成电路
页数 文件大小 规格书
58页 560K
描述
4M (512K X 8/256K X 16) BIT

MBM29LV400BC-70PBT 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:BGA包装说明:PLASTIC, FBGA-48
针数:48Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.23Is Samacsys:N
最长访问时间:70 ns其他特性:MINIMUM 100,000 PROGRAM/ERASE CYCLES
备用内存宽度:8启动块:BOTTOM
命令用户界面:YES数据轮询:YES
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PBGA-B48
JESD-609代码:e0长度:8 mm
内存密度:4194304 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
部门数/规模:1,2,1,7端子数量:48
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
电源:3.3 V编程电压:3 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:1.2 mm部门规模:16K,8K,32K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.035 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM切换位:YES
类型:NOR TYPE宽度:6 mm
Base Number Matches:1

MBM29LV400BC-70PBT 数据手册

 浏览型号MBM29LV400BC-70PBT的Datasheet PDF文件第2页浏览型号MBM29LV400BC-70PBT的Datasheet PDF文件第3页浏览型号MBM29LV400BC-70PBT的Datasheet PDF文件第4页浏览型号MBM29LV400BC-70PBT的Datasheet PDF文件第5页浏览型号MBM29LV400BC-70PBT的Datasheet PDF文件第6页浏览型号MBM29LV400BC-70PBT的Datasheet PDF文件第7页 
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20862-3E  
FLASH MEMORY  
CMOS  
4M (512K × 8/256K × 16) BIT  
MBM29LV400TC-70/-90/-12/MBM29LV400BC-70/-90/-12  
FEATURES  
• Single 3.0 V read, program, and erase  
Minimizes system level power requirements  
• Compatible with JEDEC-standard commands  
Uses same software commands as E2PROMs  
• Compatible with JEDEC-standard world-wide pinouts  
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)  
44-pin SOP (Package suffix: PF)  
48-pin CSOP (Package suffix: PCV)  
48-ball FBGA (Package suffix: PBT)  
• Minimum 100,000 program/erase cycles  
• High performance  
70 ns maximum access time  
• Sector erase architecture  
One 8K word, two 4K words, one 16K word, and seven 32K words sectors in word mode  
One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes sectors in byte mode  
Any combination of sectors can be concurrently erased. Also supports full chip erase  
• Boot Code Sector Architecture  
T = Top sector  
B = Bottom sector  
• Embedded EraseTM Algorithms  
Automatically preprograms and erases the chip or any sector  
• Embedded ProgramTM Algorithms  
Automatically writes and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Ready/Busy output (RY/BY)  
Hardware method for detection of program or erase cycle completion  
• Automatic sleep mode  
When addresses remain stable, automatically switch themselves to low power mode  
• Low VCC write inhibit 2.5 V  
• Erase Suspend/Resume  
Suspends the erase operation to allow a read in another sector within the same device  
(Continued)  
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  

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