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MBM29LV002TC-90PTR PDF预览

MBM29LV002TC-90PTR

更新时间: 2024-11-07 23:05:43
品牌 Logo 应用领域
富士通 - FUJITSU 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
52页 418K
描述
2M (256K x 8) BIT

MBM29LV002TC-90PTR 技术参数

是否Rohs认证:不符合生命周期:Transferred
零件包装代码:TSOP1包装说明:PLASTIC, REVERSE, TSOP1-40
针数:40Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.38Is Samacsys:N
最长访问时间:90 ns其他特性:MINIMUM 100000 PROGRAM/ERASE CYCLES
启动块:TOP命令用户界面:YES
数据轮询:YESJESD-30 代码:R-PDSO-G40
JESD-609代码:e0长度:18.4 mm
内存密度:2097152 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
部门数/规模:1,2,1,3端子数量:40
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1-R
封装等效代码:TSSOP40,.8,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:3/3.3 V编程电压:3 V
认证状态:Not Qualified就绪/忙碌:YES
反向引出线:YES座面最大高度:1.2 mm
部门规模:16K,8K,32K,64K最大待机电流:0.000005 A
子类别:Flash Memories最大压摆率:0.035 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
切换位:YES类型:NOR TYPE
宽度:10 mmBase Number Matches:1

MBM29LV002TC-90PTR 数据手册

 浏览型号MBM29LV002TC-90PTR的Datasheet PDF文件第2页浏览型号MBM29LV002TC-90PTR的Datasheet PDF文件第3页浏览型号MBM29LV002TC-90PTR的Datasheet PDF文件第4页浏览型号MBM29LV002TC-90PTR的Datasheet PDF文件第5页浏览型号MBM29LV002TC-90PTR的Datasheet PDF文件第6页浏览型号MBM29LV002TC-90PTR的Datasheet PDF文件第7页 
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20863-3E  
FLASH MEMORY  
CMOS  
2M (256K × 8) BIT  
MBM29LV002TC-70/-90/-12/MBM29LV002BC-70/-90/-12  
FEATURES  
• Single 3.0 V read, program, and erase  
Minimizes system level power requirements  
• Compatible with JEDEC-standard commands  
Uses same software commands as E2PROMs  
• Compatible with JEDEC-standard world-wide pinouts  
40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type)  
40-pin SON (Package suffix: PNS)  
• Minimum 100,000 program/erase cycles  
• High performance  
70 ns maximum access time  
• Sector erase architecture  
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes  
Any combination of sectors can be concurrently erased. Also supports full chip erase  
• Boot Code Sector Architecture  
T = Top sector  
B = Bottom sector  
• Embedded EraseTM Algorithms  
Automatically pre-programs and erases the chip or any sector  
• Embedded ProgramTM Algorithms  
Automatically writes and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Ready/Busy output (RY/BY)  
Hardware method for detection of program or erase cycle completion  
• Automatic sleep mode  
When addresses remain stable, automatically switch themselves to low power mode  
• Low VCC write inhibit 2.5 V  
• Erase Suspend/Resume  
Suspends the erase operation to allow a read data in another sector within the same device  
• Sector protection  
Hardware method disables any combination of sectors from program or erase operations  
• Sector Protection Set function by Extended sector protection command  
• Temporary sector unprotection  
Temporary sector unprotection via the RESET pin  
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  

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