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MBM29LV001BC-70 PDF预览

MBM29LV001BC-70

更新时间: 2024-09-20 22:09:27
品牌 Logo 应用领域
富士通 - FUJITSU /
页数 文件大小 规格书
49页 404K
描述
1M (128K x 8) BIT

MBM29LV001BC-70 数据手册

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FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20861-3E  
FLASH MEMORY  
CMOS  
1M (128K × 8) BIT  
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70  
FEATURES  
• Single 3.0 V read, program, and erase  
Minimizes system level power requirements  
• Compatible with JEDEC-standard commands  
Uses same software commands as E2PROMs  
• Compatible with JEDEC-standard world-wide pinouts  
32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)  
32-pin PLCC (Package suffix: PD)  
• Minimum 100,000 program/erase cycles  
• High performance  
55 ns maximum access time  
• Sector erase architecture  
One 8K byte, two 4K bytes, and seven 16K bytes  
Any combination of sectors can be concurrently erased. Also supports full chip erase  
• Boot Code Sector Architecture  
T = Top sector  
B = Bottom sector  
• Embedded EraseTM Algorithms  
Automatically pre-programs and erases the chip or any sector  
• Embedded ProgramTM Algorithms  
Automatically writes and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Hardware RESET pin  
Resets internal state machine to the read mode  
• Automatic sleep mode  
When addresses remain stable, automatically switch themselves to low power mode  
• Low VCC write inhibit 2.5 V  
• Erase Suspend/Resume  
Suspends the erase operation to allow a read data in another sector within the same device  
• Sector protection  
Hardware method disables any combination of sectors from program or erase operations  
• Sector Protection Set function by Extended sector protection command  
• Temporary sector unprotection  
Temporary sector unprotection via the RESET pin  
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  

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