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MBM29F200BC-55PF PDF预览

MBM29F200BC-55PF

更新时间: 2024-11-03 22:07:03
品牌 Logo 应用领域
富士通 - FUJITSU 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
48页 490K
描述
2M (256K X 8/128K X 16) BIT

MBM29F200BC-55PF 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP44,.63
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.26Is Samacsys:N
最长访问时间:55 ns其他特性:MINIMUM 100000 PROGRAM/ERASE CYCLES; ALSO CONFIGURABLE AS 128K X 16
备用内存宽度:8启动块:BOTTOM
命令用户界面:YES数据轮询:YES
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:28.45 mm
内存密度:2097152 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
部门数/规模:1,2,1,3端子数量:44
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP44,.63封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V编程电压:5 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:2.5 mm部门规模:16K,8K,32K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.05 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL切换位:YES
类型:NOR TYPE宽度:13 mm
Base Number Matches:1

MBM29F200BC-55PF 数据手册

 浏览型号MBM29F200BC-55PF的Datasheet PDF文件第2页浏览型号MBM29F200BC-55PF的Datasheet PDF文件第3页浏览型号MBM29F200BC-55PF的Datasheet PDF文件第4页浏览型号MBM29F200BC-55PF的Datasheet PDF文件第5页浏览型号MBM29F200BC-55PF的Datasheet PDF文件第6页浏览型号MBM29F200BC-55PF的Datasheet PDF文件第7页 
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20867-3E  
FLASH MEMORY  
CMOS  
2M (256K × 8/128K × 16) BIT  
MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90  
FEATURES  
• Single 5.0 V read, write, and erase  
Minimizes system level power requirements  
• Compatible with JEDEC-standard commands  
Uses same software commands as E2PROMs  
• Compatible with JEDEC-standard world-wide pinouts  
48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)  
44-pin SOP (Package suffix: PF)  
• Minimum 100,000 write/erase cycles  
• High performance  
55 ns maximum access time  
• Sector erase architecture  
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.  
Any combination of sectors can be concurrently erased. Also supports full chip erase.  
• Boot Code Sector Architecture  
T = Top sector  
B = Bottom sector  
• Embedded EraseTM Algorithms  
Automatically pre-programs and erases the chip or any sector  
• Embedded ProgramTM Algorithms  
Automatically writes and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Ready/Busy output (RY/BY)  
Hardware method for detection of program or erase cycle completion  
• Low Vcc write inhibit 3.2 V  
• Erase Suspend/Resume  
Suspends the erase operation to allow a read in another sector within the same device  
• Hardware RESET pin  
Resets internal state machine to the read mode  
• Sector protection  
Hardware method disables any combination of sectors from write or erase operations  
• Temporary sector unprotection  
Hardware method temporarily enables any combination of sectors from write on erase operations.  
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  

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