Datasheet > MB9BF314NPMC-JNE2

MB9BF314NPMC-JNE2

更新时间： 2024-11-12 10:33:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器
页数	文件大小	规格书
117页	3574K
描述
RISC Microcontroller, CMOS

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MB9B310R Series

32-bit ARM^®Cortex^®-M3 based

FM3 Microcontroller

The MB9B310R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance

and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has

peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I²C, LIN). The

products which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual.

Features

External Bus Interface

32-bit ARM Cortex-M3 Core

Supports SRAM, NOR and NAND Flash device

Processor version: r2p1

Up to 8 chip selects

Up to 144MHz Frequency Operation

8-/16-bit Data width

Memory Protection Unit (MPU): improves the reliability of an

Up to 25-bit Address bit

embedded system

Maximum area size : Up to 256 Mbytes

Supports Address/Data multiplex

Supports external RDY input

Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

24-bit System timer (Sys Tick): System timer for OS task

management

USB Interface

On-chip Memories

USB interface is composed of Device and Host.

PLL for USB is built-in, USB clock can be generated by

multiplication of Main clock.

Flash memory

These series are based on two independent on-chip Flash

memories.

−

USB device

−

MainFlash

 USB2.0 Full-Speed supported

 Max 6 EndPoint supported

• EndPoint 0 is control transfer

• EndPoint 1, 2 can be selected Bulk-transfer,

Interrupt-transfer or Isochronous-transfer

• EndPoint 3 to 5 can be selected Bulk-transfer or

Interrupt-transfer

• EndPoint 1 to 5 is comprised Double Buffer

• The size of each EndPoint is as follows.

• EndPoint 0, 2 to 5:64 bytes

• EndPoint 1: 256 bytes

 Up to 512 Kbyte

 Built-in Flash Accelerator System with 16 Kbyte trace

buffer memory

 The read access to Flash memory can be achieved without

wait cycle up to operation frequency of

 72 MHz. Even at the operation frequency more than 72

MHz, an equivalent access to Flash memory can be

obtained by Flash Accelerator System.

 Security function for code protection

−

WorkFlash

 32 Kbyte

 Read cycle

−

USB host

 4wait-cycle: the operation frequency more than 72 MHz

 2wait-cycle: the operation frequency more than 40 MHz,

and to 72 MHz

 0wait-cycle: the operation frequency to 40 MHz

 Security function is shared with code protection

 USB2.0 Full/Low-speed supported

 Bulk-transfer, interrupt-transfer and Isochronous-transfer

support

 USB Device connected/dis-connected automatically detect

 IN/OUT token handshake packet automatically

 Max 256-byte packet-length supported

SRAM

 Wake-up function supported

This Series contain a total of up to 64 Kbyte on-chip SRAM.

This is composed of two independent SRAM (SRAM0,

SRAM1). SRAM0 is connected to I-code bus and D-code bus

of Cortex-M3 core. SRAM1 is connected to System bus.

 SRAM0: Up to 32 Kbyte

 SRAM1: Up to 32 Kbyte

Cypress Semiconductor Corporation

Document Number: 002-05619 Rev.*A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 17, 2016

12 3 4 5 6 7...117

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与MB9BF314NPMC-JNE2相关器件

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MB9BF314R	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF314RPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3FM3 Microcontroller
MB9BF314RPMC-JNE2	CYPRESS	获取价格	RISC Microcontroller, CMOS
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MB9BF315NBGL-GE1	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3FM3 Microcontroller
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