Datasheet > MB9BF114NPMC-G-JNE2

MB9BF114NPMC-G-JNE2

更新时间： 2024-09-17 19:41:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器外围集成电路
页数	文件大小	规格书
117页	1789K
描述
RISC Microcontroller, CMOS,

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MB9BF114NPMC-G-JNE2 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01	风险等级：	5.72
峰值回流温度（摄氏度）：	NOT SPECIFIED	技术：	CMOS
处于峰值回流温度下的最长时间：	NOT SPECIFIED	uPs/uCs/外围集成电路类型：	MICROCONTROLLER, RISC
Base Number Matches：	1

MB9BF114NPMC-G-JNE2 数据手册

浏览型号MB9BF114NPMC-G-JNE2的Datasheet PDF文件第2页

浏览型号MB9BF114NPMC-G-JNE2的Datasheet PDF文件第3页

浏览型号MB9BF114NPMC-G-JNE2的Datasheet PDF文件第4页

浏览型号MB9BF114NPMC-G-JNE2的Datasheet PDF文件第5页

浏览型号MB9BF114NPMC-G-JNE2的Datasheet PDF文件第6页

浏览型号MB9BF114NPMC-G-JNE2的Datasheet PDF文件第7页

MB9B110R Series

32-bit ARM^®Cortex^®-M3

FM3 Microcontroller

The MB9B110R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance

and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has

peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I²C, LIN). The products

which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual.

External Bus Interface

Supports SRAM, NOR and NAND Flash device

Features

32-bit ARM Cortex-M3 Core

Processor version: r2p1

Up to 8 chip selects

8-/16-bit Data width

Up to 25-bit Address bit

Up to 144 MHz Frequency Operation

Maximum area size: Up to 256 Mbytes

Supports Address/Data multiplex

Supports external RDY input

Memory Protection Unit (MPU): improves the reliability of an

embedded system

Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

Multi-function Serial Interface (Max eight channels)

4 channels with 16 steps×9-bit FIFO (ch.4-ch.7), 4 channels

without FIFO (ch.0-ch.3)

24-bit System timer (Sys Tick): System timer for OS task

management

Operation mode is selectable from the followings for each

channel.

 UART

 CSIO

 LIN

On-chip Memories

[Flash memory]

These series are based on two independent on-chip Flash

 I²C

memories.

UART

 Full-duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Hardware Flow control : Automatically control the

transmission by CTS/RTS (only ch.4)

 Various error detect functions available (parity errors,

framing errors, and overrun errors)

MainFlash

 Up to 512 Kbyte

 Built-in Flash Accelerator System with 16 Kbyte trace buffer

memory

 The read access to Flash memory can be achieved without

wait cycle up to operation frequency of 72 MHz. Even at the

operation frequency more than 72 MHz, an equivalent

access to Flash memory can be obtained by Flash

Accelerator System.

 Security function for code protection

CSIO

 Full-duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detect function available

WorkFlash

 32 Kbyte

 Read cycle

 4 wait-cycle: the operation frequency more than 72 MHz

 2 wait-cycle: the operation frequency more than 40 MHz, and

to 72 MHz

 0wait-cycle: the operation frequency to 40 MHz

 Security function is shared with code protection

LIN

 LIN protocol Rev.2.1 supported

 Full-duplex double buffer

 Master/Slave mode supported

 LIN break field generate (can be changed 13 to 16-bit

length)

 LIN break delimiter generate (can be changed 1 to 4-bit

length)

 Various error detect functions available (parity errors,

framing errors, and overrun errors)

[SRAM]

This Series contain a total of up to 64 Kbyte on-chip SRAM.

This is composed of two independent SRAM (SRAM0,

SRAM1). SRAM0 is connected to I-code bus and D-code bus

I²C

of Cortex-M3 core. SRAM1 is connected to System bus.

 SRAM0: Up to 32 Kbyte

 SRAM1: Up to 32 Kbyte

 Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)

supported

Cypress Semiconductor Corporation

Document Number: 002-05622 Rev.*C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 21, 2017

12 3 4 5 6 7...117

中文翻译

下载PDF

与MB9BF114NPMC-G-JNE2相关器件

型号	品牌	获取价格	描述	数据表
MB9BF114NPQC-G-JNE2	CYPRESS	获取价格	RISC Microcontroller, CMOS,
MB9BF114R	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF114RPMC	CYPRESS	获取价格	RISC Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 144MHz, CMOS, PQFP120, LQFP-120
MB9BF114RPMC-G-JNE2	CYPRESS	获取价格	RISC Microcontroller, CMOS,
MB9BF115N	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF115NBGL-GE1	CYPRESS	获取价格	RISC Microcontroller, CMOS,
MB9BF115NPMC	SPANSION	获取价格	RISC Microcontroller, 32-Bit, FLASH, 144MHz, CMOS, PQFP100, LQFP-100
MB9BF115NPMC-G-JNE2	CYPRESS	获取价格	RISC Microcontroller, CMOS,
MB9BF115NPQC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF115R	SPANSION	获取价格	This document states the current technical specifications regarding

与MB9BF114NPMC-G-JNE2相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

15
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

14
SL74HC10N：高性能三输入与非门解析
2024-09-03

93
AIC1781A 电池充电控制器深度解析
2024-09-03

82

产品中心

服务支持

精选活动

关于我们

帮助中心

MB9BF114NPMC-G-JNE2

MB9BF114NPMC-G-JNE2 技术参数

MB9BF114NPMC-G-JNE2 数据手册

与MB9BF114NPMC-G-JNE2相关器件

与MB9BF114NPMC-G-JNE2相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MB9BF114NPMC-G-JNE2

MB9BF114NPMC-G-JNE2 技术参数

MB9BF114NPMC-G-JNE2 数据手册

与MB9BF114NPMC-G-JNE2相关器件

与MB9BF114NPMC-G-JNE2相关文章

您还可以找

您在本页遇到什么问题？