Datasheet > MB9BF102NABGL-GK6E1

MB9BF102NABGL-GK6E1

更新时间： 2024-11-06 00:42:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器
页数	文件大小	规格书
109页	1991K
描述
32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller

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MB9B100A Series

32-bit Arm^®Cortex^®-M3

FM3 Microcontroller

The MB9B100A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded

control applications.

The MB9B100ASeries are based on theArm^®Cortex^®-M3 Processor and on-chip Flash memory and SRAM, and peripheral functions,

including Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I²C, LIN).

The products which are described in this data sheet are placed into TYPE0 product categories in "FM3 Family PERIPHERAL

MANUAL".

Features

32-bit Arm^®Cortex^®-M3 Core

Multi-function Serial Interface (Max. 8 channels)

Processor version: r2p0

4 channels with 16 steps × 9bit FIFO (ch.4-ch.7), 4 channels

without FIFO (ch.0-ch.3)

Up to 80 MHz Frequency Operation

Operation mode is selectable from the followings for each

Memory Protection Unit (MPU): improve the reliability of an

channel.

 UART

 CSIO

 LIN

embedded system

Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

 I²C

24-bit System timer (Sys Tick): System timer for OS task

management

[UART]

Full-duplex double buffer

On-chip Memories

Selection with or without parity supported

Built-in dedicated baud rate generator

External clock available as a serial clock

[Flash memory]

Up to 512 Kbyte

Read cycle: 0 wait-cycle@up to 60 MHz, 2 wait-cycle* above

*: Instruction pre-fetch buffer is included. So when CPU

access continuously, it becomes 0wait-cycle

Hardware Flow control: Automatically control the

transmission by CTS/RTS (only ch.4)

Various error detect functions available (parity errors,

framing errors, and overrun errors)

Security function for code protection

[SRAM]

[CSIO]

This series contain a total of up to 64 Kbyte on-chip SRAM.

This is composed of two independent SRAM(SRAM0,

SRAM1). SRAM0 is connected to I-code bus and D-code bus

of Cortex-M3 core. SRAM1 is connected to System bus.

Full-duplex double buffer

Built-in dedicated baud rate generator

Overrun error detect function available

SRAM0: Up to 32 Kbyte

SRAM1: Up to 32 Kbyte

[LIN]

LIN protocol Rev.2.1 supported

Full-duplex double buffer

Master/Slave mode supported

LIN break field generate (can be changed 13-16bit length)

LIN break delimiter generate (can be changed 1-4bit length)

Various error detect functions available (parity errors,

framing errors, and overrun errors)

Cypress Semiconductor Corporation

Document Number: 002-05605 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 15, 2017

12 3 4 5 6 7...109

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与MB9BF102NABGL-GK6E1相关器件

型号	品牌	获取价格	描述	数据表
MB9BF102NAPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF102NBGL-GE1	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF102NPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF102RA	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF102RAPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF102RPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF104NA	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF104NABGL-GK6E1	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF104NAPMC-G-JNE2	CYPRESS	获取价格	RISC Microcontroller, CMOS,
MB9BF104NAPMC-G-UNE1	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller

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