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MB95F652LWQN-G-SNERE1 PDF预览

MB95F652LWQN-G-SNERE1

更新时间: 2024-11-21 00:35:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
105页 12176K
描述
F2MC-8FX CPU core

MB95F652LWQN-G-SNERE1 数据手册

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MB95650L Series  
New 8FX 8-bit Microcontrollers  
The MB95650L Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the  
microcontrollers of this series contain a variety of peripheral functions.  
Features  
2
2
F MC-8FX CPU core  
I Cbusinterface2channels(Oneofthetwochannels  
2
can be used either as an I C bus interface channel or  
as a UART/SIO channel.)  
Instruction set optimized for controllers  
Multiplication and division instructions  
16-bit arithmetic operations  
Supports Standard-mode and Fast-mode (400 kHz).  
Built-in wake-up function  
Bit test branch instructions  
LIN-UART  
Bit manipulation instructions, etc.  
Full duplex double buffer  
Clock  
Capable of clock asynchronous serial data transfer and clock  
synchronous serial data transfer  
Selectable main clock source  
Main oscillation clock (up to 16.25 MHz, maximum machine  
clock frequency: 8.125 MHz)  
External interrupt 6 channels  
External clock (up to 32.5 MHz, maximum machine clock  
Interrupt by edge detection (rising edge, falling edge, and both  
edges can be selected)  
frequency: 16.25 MHz)  
Main CR clock (4 MHz 2%)  
Main CR PLL clock  
• The main CR PLL clock frequency becomes 8 MHz 2%  
when the PLL multiplication rate is 2.  
• The main CR PLL clock frequency becomes 10 MHz 2%  
when the PLL multiplication rate is 2.5.  
Can be used to wake up the device from different low power  
consumption (standby) modes  
8/12-bit A/D converter 6 channels  
8-bit or 12-bit resolution can be selected.  
• The main CR PLL clock frequency becomes 12 MHz 2%  
when the PLL multiplication rate is 3.  
Low power consumption (standby) modes  
There are four standby modes as follows:  
• The main CR PLL clock frequency becomes 16 MHz 2%  
when the PLL multiplication rate is 4.  
Stop mode  
Main PLL clock (maximum machine clock frequency:  
16 MHz)  
Sleep mode  
Selectable subclock source  
Watch mode  
Suboscillation clock (32.768 kHz)  
External clock (32.768 kHz)  
Time-base timer mode  
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)  
I/O port  
MB95F652E/F653E/F654E/F656E (number of I/O ports: 21)  
Timer  
General-purpose I/O ports (CMOS I/O)  
General-purpose I/O ports (N-ch open drain)  
: 17  
: 4  
8/16-bit composite timer 2 channels  
Time-base timer 1 channel  
Watch prescaler 1 channel  
MB95F652L/F653L/F654L/F656L (number of I/O ports: 20)  
General-purpose I/O ports (CMOS I/O)  
General-purpose I/O ports (N-ch open drain)  
: 17  
: 3  
UART/SIO 1 channel (The channel can be used either  
2
as a UART/SIO channel or as an I C bus interface  
On-chip debug  
channel.)  
1-wire serial control  
The function of this channel can be switched between  
Serial writing supported (asynchronous mode)  
UART/SIO and I2C bus interface.  
Hardware/software watchdog timer  
Built-in hardware watchdog timer  
Built-in software watchdog timer  
Full duplex double buffer  
Capableofclockasynchronous(UART)serialdatatransferand  
clock synchronous (SIO) serial data transfer  
Cypress Semiconductor Corporation  
Document Number: 002-04696 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 12, 2016  

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