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MB95F616H

更新时间: 2024-11-20 00:51:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
110页 11043K
描述
F2MC-8FX CPU core

MB95F616H 数据手册

 浏览型号MB95F616H的Datasheet PDF文件第2页浏览型号MB95F616H的Datasheet PDF文件第3页浏览型号MB95F616H的Datasheet PDF文件第4页浏览型号MB95F616H的Datasheet PDF文件第5页浏览型号MB95F616H的Datasheet PDF文件第6页浏览型号MB95F616H的Datasheet PDF文件第7页 
MB95F613H/F613K/F614H  
MB95F614K/F616H/F616K  
PRELIMINARY  
New 8FX MB95610H Series  
8-bit Microcontrollers  
The MB95610H Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the  
microcontrollers of these series contain a variety of peripheral resources.  
Features  
F2MC-8FX CPU core  
Instruction set optimized for controllers  
Capableofclockasynchronous(UART)serialdatatransferand  
clock synchronous (SIO) serial data transfer  
I2C bus interface 1 channel  
Multiplication and division instructions  
Built-in wake-up function  
16-bit arithmetic operations  
External interrupt 8 channels  
Bit test branch instructions  
Interrupt by edge detection (rising edge, falling edge, and both  
edges can be selected)  
Bit manipulation instructions, etc.  
Clock  
Can be used to wake up the device from different low power  
consumption (standby) modes  
Selectable main clock source  
8/10-bit A/D converter 4 channels  
8-bit or 10-bit resolution can be selected.  
LCD controller (LCDC)  
Main oscillation clock (up to 16.25 MHz, maximum machine  
clock frequency: 8.125 MHz)  
External clock (up to 32.5 MHz, maximum machine clock  
frequency: 16.25 MHz)  
Main CR clock (4 MHz 2%)  
Main PLL clock / Main CR PLL clock (Main oscillation clock  
= 4 MHz, Main CR clock = 4 MHz)  
LCD output can be selected from 52 SEG 4 COM or 48 SEG  
8 COM.  
• Both main oscillation clock and main CR clock can be mul-  
tiplied by a PLL multiplication rate.  
Internaldividerresistorwhoseresistancevaluecanbeselected  
from 10 kor 100 kthrough software  
• The frequency of the main PLL clock / main CR PLL clock  
becomes 8 MHz when the PLL multiplication rate is 2.  
• he frequency of the main PLL clock / main CR PLL clock  
becomes 10 MHz when the PLL multiplication rate is 2.5.  
• he frequency of the main PLL clock / main CR PLL clock  
becomes 12 MHz when the PLL multiplication rate is 3.  
• he frequency of the main PLL clock / main CR PLL clock  
becomes 16 MHz when the PLL multiplication rate is 4.  
Interrupt in sync with the LCD module frame frequency  
Blinking function  
Inverted display function  
Low power consumption (standby) modes  
There are four standby modes as follows:  
Stop mode  
Selectable subclock source  
Suboscillation clock (32.768 kHz)  
External clock (32.768 kHz)  
Sleep mode  
Watch mode  
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)  
Time-base timer mode  
In standby mode, two further options can be selected: normal  
standby mode and deep standby mode.  
Timer  
I/O port  
8/16-bit composite timer 2 channels  
8/16-bit PPG 2 channels  
16-bit reload timer 1 channel  
Event counter 1 channel  
Time-base timer 1 channel  
Watch counter 1 channel  
Watch prescaler 1 channel  
UART/SIO 2 channels  
Full duplex double buffer  
MB95F613H/F614H/F616H (no. of I/O ports: 40)  
General-purpose I/O ports (CMOS I/O): 39  
General-purpose I/O ports (N-ch open drain): 1  
MB95F613K/F614K/F616K (no. of I/O ports: 41)  
General-purpose I/O ports (CMOS I/O): 39  
General-purpose I/O ports (N-ch open drain): 2  
On-chip debug  
1-wire serial control  
Serial writing supported (asynchronous mode)  
Cypress Semiconductor Corporation  
Document Number: 002-04698 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 8, 2016  

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