19-1534; Rev 1; 10/99
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
General Description
Features
ꢀ +3.3V Single Supply
The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±±.ꢀns sꢁew between any parallel
data input and the reference clocꢁ. An external
1ꢀꢀMHz reference clocꢁ is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clocꢁ for tim-
ing the outgoing data streams.
ꢀ 1.45W Power Dissipation (MAX3831)
ꢀ 4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock Generator
ꢀ Frame Detection Maintains Channel Assignment
ꢀ ±±.5ns ꢀlastic Store ꢁange
ꢀ 2.5ps ꢁMS Serial-Data Output ꢁandom Jitter
ꢀ 8ps Serial-Data Output Deterministic Jitter
ꢀ 622Mbps LVDS Parallel Input/Output
ꢀ 2.488Gbps Serial CML Input/Output
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clocꢁ from an external
clocꢁ/data recovery device (MAX38±6), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clocꢁ output, and the MAX3832 pro-
vides a 1ꢀꢀMHz LVDS clocꢁ output. An internal frame
detector looꢁs for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
ꢀ On-Chip Pattern Generator Provides
High-Speed BIST
ꢀ System Test Flexibility: System Loopback,
Line Loopback
ꢀ Loss-of-Frame Indicator
Applications
ATM Switching Networꢁs
SDH/SONET Bacꢁplanes
High-Speed Parallel Linꢁs Line Extenders
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopbacꢁ modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) pacꢁages and are specified over the
upper commercial (0°C to +8ꢀ°C) temperature range.
Intraracꢁ/Subracꢁ
Interconnects
Dense Digital Cross-
Connects
Ordering Information
PAꢁT
TꢀMP. ꢁANGꢀ
0°C to +8ꢀ°C
0°C to +8ꢀ°C
PIN-PACKAGꢀ
64 TQFP-EP
MAX3831UCB
MAX3832UCB
Pin Configuration appears at end of data sheet.
64 TQFP-EP
Typical Application Circuit
+3.3V
0.33µF
TTL
TTL
TTL
TTL
0.1µF
RSETES
RCLKI+
RCLKI-
FIL+ FIL- TEST
LOF PLBEN
V
CC
155MHz REF
SCLKI-
SCLKI+
SDI-
LVDS
LVDS
CML
CLOCK INPUT
MAX3876
2.5Gbps
CDR
4
4
PDI1+ TO PDI4+
2.5Gbps
OPTICAL
TRANSCEIVER
CML
PDI1- TO PDI4-
SDI+
MAX3831
MAX3832
4
4
CMOS
OVERHEAD
PDO1+ TO PDO4+
PDO1- TO PDO4-
PCLKO+
SDO+
SDO-
LVDS
LVDS
TTL
TTL
LBEN
PCLKO-
GND
RSETFR
TRIEN
TTL
________________________________________________________________ Maxim Integrated Products
1
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