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DS31406

更新时间： 2024-01-04 04:43:19

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
5页	125K
描述
2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter

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DS31406 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA,	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.28	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	长度：	17 mm
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.7 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	17 mm	Base Number Matches：	1

DS31406 数据手册

ABRIDGED DATA SHEET

19-5711; Rev 0; 12/10

DS31406

2-Input, 14-Output, Single DPLL Timing IC

with Sub-ps Output Jitter

General Description

Features



Two Input Clocks

The DS31406 is a flexible, high-performance timing IC

for diverse frequency conversion and frequency

synthesis applications. On each of its two input clocks

and fourteen output clocks, the device can accept or

generate nearly any frequency between 2kHz and

750MHz.



Differential or CMOS/TTL Format

Any Frequency from 2kHz to 750MHz

Fractional Scaling for 64B/66B and FEC Scaling

(e.g., 64/66, 237/255, 238/255) or Any Other

Downscaling Requirement



Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Two 2/4/8kHz Frame Sync Inputs

The input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for the

rest of the device. A flexible, high-performance digital

PLL locks to the selected reference and provides

programmable bandwidth, very high resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLL is followed by a clock synthesis

subsystem which has seven fully programmable digital

frequency synthesis blocks, three high-speed low-jitter

APLLs, and 14 output clocks, each with its own 32-bit

divider and phase adjustment. The APLLs provide

fractional scaling and output jitter less than 1ps RMS.



High-Performance DPLL



Hitless Reference Switching on Loss of Input

Automatic or Manual Phase Build-Out

Holdover on Loss of All Inputs

Programmable Bandwidth, 0.5mHz to 400Hz



Seven Digital Frequency Synthesizers

 Produce Any 2kHz Multiple Up to 77.76MHz

 Per-DFS Clock Phase Adjust

Three Output APLLs

 Output Frequencies to 750MHz

 High Resolution Fractional Scaling for FEC and

64B/66B (e.g., 255/237, 255/238, 66/64) or Any

Other Scaling Requirement

For telecom systems, the DS31406 has all required

features and functions to serve as a central timing

function or as a line card timing IC. With a suitable

oscillator the DS31406 meets the requirements of

Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813,

and G.8262.

 Less than 1ps RMS Output Jitter

 Simultaneously Produce Three Low-Jitter Rates from

the Same Reference (e.g., 622.08MHz for SONET,

255/237*622.08MHz for OTU2, and 156.25MHz for

10GE)



14 Output Clocks in Seven Groups

Applications

 Nearly Any Frequency from <1Hz to 750MHz

 Each Group Slaves to a DFS Clock, Any APLL

Clock, or Any Input Clock (Divided and Scaled)

 Each Has a Differential Output (3 CML, 4 LVDS/

LVPECL) and Separate CMOS/TTL Output

 32-Bit Frequency Divider Per Output

Frequency Conversion Applications in a Wide Variety of

Equipment Types

Telecom Line Cards or Timing Cards with Any Mix of

SONET/SDH, Synchronous Ethernet and/or OTN

Ports in WAN Equipment Including MSPPs, Ethernet

Switches, Routers, DSLAMs, and Base Stations

 Two Sync Pulse Outputs: 8kHz and 2kHz

General Features

Ordering Information

 Suitable Line Card IC or Timing Card IC for

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

 Accepts and Produces Nearly Any Frequency Up

to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1,

NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M,

156.25M, and Nx19.44M Up to 622.08M

 Internal Compensation for Local Oscillator

Frequency Error

PART

TEMP RANGE

PIN-PACKAGE

DS31406GN+

256 CSBGA

-40C to +85C

+Denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

 SPI™ Processor Interface



1.8V Operation with 3.3V I/O (5V Tolerant)

Maxim Integrated Products

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device

errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

12 3 4 5

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与DS31406相关器件

型号	品牌	描述	获取价格	数据表
DS31406GN+	MAXIM	2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter	获取价格
DS31407	MAXIM	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter Differential	获取价格
DS31407	MICROCHIP	The DS31407 is a flexible, high-performance timing IC for diverse frequency conversion and	获取价格
DS31407GN+	MAXIM	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter Differential	获取价格
DS31408	MAXIM	8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock	获取价格
DS31408	MICROCHIP	The DS31408 is a flexible, high-performance timing IC for diverse frequency conversion and	获取价格

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