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DS1WM

更新时间: 2024-01-08 18:49:17
品牌 Logo 应用领域
美信 - MAXIM 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
页数 文件大小 规格书
20页 118K
描述
Synthesizable 1-Wire Bus Master

DS1WM 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.62Base Number Matches:1

DS1WM 数据手册

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DS1WM  
Synthesizable 1-Wire Bus Master  
www.maxim-ic.com  
FEATURES  
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Memory maps into any standard byte-wide data  
bus.  
Customer ASIC  
Eliminates CPU “bit-banging” by internally  
generating all 1-Wire timing and control signals.  
Generates interrupts to provide for more efficient  
programming.  
Search ROM Accelerator relieves CPU from any  
single bit operations on the 1-Wire® Bus.  
Capable of running off any system clock from 4  
MHz to 128 MHz.  
1-Wire  
Bus  
1-WireTM  
Master  
Internal  
Data Bus  
Strong  
Pull-up  
control  
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Small size: all digital design, only 3470 gates.  
Applications include any circuit containing a 1-  
Wire communication bus.  
Interrupt  
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Supports standard and overdrive 1-Wire  
communication speeds  
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Supports strong pull-up specifications.  
Master available in both Verilog and VHDL  
Supports single bit transmissions.  
Provides added support for long line conditions.  
DESCRIPTION  
As more 1-Wire devices become available, more and more users have to deal with the demands of  
generating 1-Wire signals to communicate to them. This usually requires “bit-banging” a port pin on a  
microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire  
protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the  
“low” time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit  
sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle  
communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a  
user’s ASIC as a 1-Wire port, the Verilog or VHDL core uses little chip area (3470 gates plus 2 bond  
pads).  
This circuit is designed to be memory mapped into the user’s system and provides complete control of the  
1-Wire bus through 8-bit or single commands. The host CPU loads commands, reads and writes data, and  
sets interrupt control through six individual registers. All of the timing and control of the 1-Wire bus are  
generated within. The host merely needs to load a command or data and then may go on about its  
business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master  
sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read  
simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU  
from having to perform the complex single-bit operations on the 1-Wire bus.  
1-Wire is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc.  
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