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MAX9687C/D

更新时间： 2024-09-21 22:38:35
品牌 Logo 应用领域
美信 - MAXIM 比较器
页数 文件大小 规格书
4页 47K
描述
Dual, Ultra-Fast ECL-Output Comparator

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MAX9687C/D 数据手册

 浏览型号MAX9687C/D的Datasheet PDF文件第2页浏览型号MAX9687C/D的Datasheet PDF文件第3页浏览型号MAX9687C/D的Datasheet PDF文件第4页 
19-2400; Rev 1; 7/93  
Du a l, Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
MAX9687  
_______________Ge n e ra l De s c rip t io n  
The MAX9687 is a d ua l, ultra -fa s t ECL c omp a ra tor  
manufactured with a high-frequency bipolar process  
____________________________Fe a t u re s  
♦ 1.4ns Propagation Delay  
(f = 6GHz) capable of very short propagation delays.  
T
♦ 0.5ns Latch Setup Time  
This design maintains the excellent DC matching char-  
acteristics normally found only in slower comparators.  
♦ 2.0ns Latch-Enable Pulse Width  
♦ +5V, -5.2V Power Supplies  
The MAX9687 is pin-compatible with the AD9687 and  
Am6687, but exceeds their AC characteristics.  
♦ Pin-Compatible with AD9687, Am6687, SP9687  
The MAX9687 has differential inputs and complemen-  
tary outputs that are fully compatible with ECL-logic lev-  
els. Output current levels are capable of driving 50Ω  
terminated transmission lines. The ultra-fast operation  
makes signal processing possible at frequencies in  
excess of 600MHz.  
♦ Available in Commercial, Extended-Industrial,  
and Military Temperature Ranges  
♦ Available in Narrow SO Package  
A latch-enable (LE) function is provided to allow the  
comparator to be used in a sample/hold or track/hold  
mode. The latch-enable inputs are designed to be dri-  
______________Ord e rin g In fo rm a t io n  
PART  
TEMP. RANGE  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
-40°C to +85°C  
-40°C to +85°C  
-55°C to +125°C  
PIN-PACKAGE*  
16 Plastic DIP  
16 Narrow SO  
16 CERDIP  
ven from the complementary outputs of a standard ECL  
–—–  
MAX9687CPE  
MAX9687CSE  
MAX9687CJE  
MAX9687C/D  
MAX9687EPE  
MAX9687ESE  
MAX9687MJE  
gate. When LE is high and LE is low, the comparator  
–—–  
functions normally. When LE is forced low and LE is  
high, the comparator outputs are locked in the logical  
states determined by the input conditions at the time of  
the latch transition. If the latch-enable function is not  
used on either of the two comparators, the appropriate  
Dice**  
16 Plastic DIP  
16 Narrow SO  
16 CERDIP  
LE input must be connected to ground; the companion  
–—–  
LE input can be left open.  
*
Contact factory for availability of 20-pin PLCC.  
________________________Ap p lic a t io n s  
** Contact factory for dice specifications.  
High-Speed A/D Converters  
High-Speed Line Receivers  
Peak Detectors  
Threshold Detectors  
High-Speed Triggers  
___________________P in Co n fig u ra t io n  
________________Fu n c t io n a l Dia g ra m  
TOP VIEW  
NONINVERTING  
INPUT  
NONINVERTING  
INPUT  
Q OUT  
Q OUT  
Q OUT  
Q OUT  
GND  
LEA  
1
2
3
4
5
6
7
8
16 Q OUT  
15 Q OUT  
14 GND  
13 LEB  
12 LEB  
11 V+  
INVERTING  
INPUT  
INVERTING  
INPUT  
A
B
R
L
R
R
R
L
L
L
LEA  
LE LE  
LE LE  
LATCH ENABLE  
V-  
V
T
LATCH ENABLE  
INA-  
10 INB-  
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULL-DOWN  
RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50Ω – 200Ω  
CONNECTED TO -2.0V, OR 240Ω – 2000Ω CONNECTED TO -5.2V.  
INA+  
9
INB+  
DIP/SO  
________________________________________________________________ Maxim Integrated Products  
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .  
1234

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