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MAX9207 PDF预览

MAX9207

更新时间: 2024-10-02 23:52:11
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描述
10-Bit.Bus LVDS Serializers

MAX9207 数据手册

 浏览型号MAX9207的Datasheet PDF文件第2页浏览型号MAX9207的Datasheet PDF文件第3页浏览型号MAX9207的Datasheet PDF文件第4页浏览型号MAX9207的Datasheet PDF文件第5页浏览型号MAX9207的Datasheet PDF文件第6页浏览型号MAX9207的Datasheet PDF文件第7页 
19-2029; Rev 0; 5/01  
10-Bit Bus LVDS Serializers  
General Description  
Features  
The MAX9205/MAX9207 serializers transform 10-bit-  
wide parallel LVCMOS/LVTTL data into a serial high-  
speed bus low-voltage differential signaling (LVDS)  
data stream. The serializers typically pair with deserial-  
izers like the MAX9206*/MAX9208*, which receive the  
serial output and transform it back to 10-bit-wide paral-  
lel data.  
Standalone Serializer (vs. SERDES) Ideal for  
Unidirectional Links  
Framing Bits for Deserializer Resync Allow Hot  
Insertion Without System Interruption  
LVDS Serial Output Rated for Point-to-Point and  
Bus Applications  
The MAX9205/MAX9207 transmit serial data at speeds  
up to 400Mbps and 660Mbps, respectively, over PC  
board traces or twisted-pair cables. Since the clock is  
recovered from the serial data stream, clock-to-data  
and data-to-data skew that would be present with a  
parallel bus are eliminated.  
Wide Reference Clock Input Range  
16MHz to 40MHz (MAX9205)  
40MHz to 66MHz (MAX9207)  
Low 140ps (pk-pk) Deterministic Jitter (MAX9207)  
Low 34mA Supply Current (MAX9205)  
The serializers require no external components and few  
control signals. The input data strobe edge is selected  
by TCLK_R/F. PWRDN is used to save power when the  
devices are not in use. Upon power-up, a synchroniza-  
tion mode is activated, which is controlled by two SYNC  
inputs, SYNC1 and SYNC2.  
10-Bit Parallel LVCMOS/LVTTL Interface  
Up to 660Mbps Payload Data Rate (MAX9207)  
Programmable Active Edge on Input Latch  
Pin-Compatible Upgrades to DS92LV1021 and  
The MAX9205 can lock to a 16MHz to 40MHz system  
clock, while the MAX9207 can lock to a 40MHz to  
66MHz system clock. The serializer output is held in  
high impedance until the device is fully locked to the  
local system clock, or when the device is in power-  
down mode.  
DS92LV1023  
Ordering Information  
TEMP.  
RANGE  
PIN-  
REF CLOCK  
PART  
Both the devices operate from a single +3.3V supply,  
are specified for operation from -40°C to +85°C, and  
are available in 28-pin SSOP packages.  
PACKAGE RANGE (MHz)  
MAX9205EAI -40 C to +85 C  
MAX9207EAI -40 C to +85 C  
28 SSOP  
28 SSOP  
16 to 40  
40 to 66  
Applications  
Cellular Phone Base  
Stations  
Add Drop Muxes  
DSLAMs  
Network Switches and  
Routers  
Pin Configuration and Functional Diagram appear at end of  
data sheet.  
Digital Cross-Connects  
Backplane Interconnect  
Typical Application Circuit  
BUS  
LVDS  
OUT+  
IN+  
10  
10  
100  
100  
OUT_  
IN_  
OUT-  
IN-  
TCLK_R/F  
TCLK  
PC BOARD OR  
TWISTED PAIR  
REFCLK  
EN  
LOCK  
EN  
TIMING AND  
CONTROL  
TIMING AND  
CONTROL  
PLL  
PLL  
PWRDN  
SYNC 1  
SYNC 2  
RCLK  
CLOCK  
RECOVERY  
MAX9205  
MAX9207  
MAX9206*  
MAX9208*  
RCLK_R/F  
*FUTURE PRODUCT  
*Future product–contact factory for availability.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  

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