19-2915; Rev 1; 10/03
Ultra-Low-Power, High-Dynamic-
Performance, 22Msps Analog Front End
General Description
Features
o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
o Ultra-Low Power
The MAX5864 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5864 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
42mW at f
34mW at f
= 22MHz (Transceiver Mode)
= 15.36MHz (Transceiver Mode)
CLK
CLK
Low-Current Idle and Shutdown Modes
o Excellent Dynamic Performance
accept 1V
full-scale signals. Typical I-Q channel
P-P
48.5dB SINAD at f = 5.5MHz (ADC)
IN
phase matching is 0.1° and amplitude matching is
71.7dB SFDR at f
= 2.2MHz (DAC)
OUT
0.03dB. The ADCs feature 48.5dB SINAD and 69dBc
spurious-free dynamic range (SFDR) at f = 5.5MHz and
IN
o Excellent Gain/Phase Match
f
= 22Msps. The DACs’ analog I-Q outputs are fully
CLK
0.1° Phase, 0.03dB Gain at f = 5.5MHz (ADC)
IN
differential with 400mV full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase match is
0.15° and amplitude match is 0.05dB. The DACs also
feature dual 10-bit resolution with 71.7dBc SFDR, and
o Internal/External Reference Option
o +1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
57dB SNR at f
= 2.2MHz and f
= 22MHz.
OUT
CLK
o Multiplexed Parallel Digital Input/Output for
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
ADCs/DACs
o Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)
o Evaluation Kit Available (Order MAX5865EVKIT)
tion. The typical operating power is 42mW at f
=
CLK
22Msps with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5864 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5864 operates on a +2.7V to +3.3V ana-
log power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
5.6mA in idle mode and 1µA in shutdown mode. The
MAX5864 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Functional Diagram
IA+
ADC
IA-
ADC
OUTPUT
MUX
DA0–DA7
CLK
QA+
QA-
ADC
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
ID+
ID-
DAC
DAC
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
DAC
INPUT
MUX
DD0–DD9
QD+
QD-
Ordering Information
REFP
COM
REFN
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
SERIAL
INTERFACE
AND SYSTEM
CONTROL
48 Thin QFN-EP*
(7mm x 7mm)
DIN
SCLK
CS
MAX5864ETM
MAX5864E/D
REF AND
BIAS
REFIN
Dice**
*EP = Exposed paddle.
**Contact factory for dice specifications.
MAX5864
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.