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MAX3620CETT PDF预览

MAX3620CETT

更新时间: 2024-11-26 04:41:59
品牌 Logo 应用领域
美信 - MAXIM 延迟线逻辑集成电路时钟
页数 文件大小 规格书
6页 160K
描述
Delay Lines for High-Speed Clock Distribution Systems

MAX3620CETT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SON
包装说明:3 X 3 MM, 0.80 MM HEIGHT, EXPOSED PAD, MO-229/WEEA, TDFN-14针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.7Is Samacsys:N
系列:3620输入频率最大值(fmax):200 MHz
JESD-30 代码:S-XDSO-N6JESD-609代码:e0
长度:3 mm逻辑集成电路类型:ACTIVE DELAY LINE
湿度敏感等级:1功能数量:2
抽头/阶步数:4端子数量:6
最高工作温度:85 °C最低工作温度:-40 °C
输出阻抗标称值(Z0):50 Ω输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:HVSON
封装等效代码:SOLCC6,.11,37封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):245
电源:+-1.5 V可编程延迟线:NO
Prop。Delay @ Nom-Sup:1.35 ns认证状态:Not Qualified
座面最大高度:0.8 mm子类别:Delay Lines
标称供电电压 (Vsup):1.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总延迟标称(td):1.25 ns宽度:3 mm
Base Number Matches:1

MAX3620CETT 数据手册

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19-3550; Rev 0; 1/05  
Delay Lines for High-Speed Clock  
Distribution Systems  
General Description  
Features  
The MAX3620 series is a family of high-performance  
passive delay lines for use in QDR/QDRII synchronous  
memory systems. These delay lines support high-speed  
transceiver logic (HSTL) source terminated transmission  
with an unterminated load at the receiver, and deliver  
accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns  
for the generation of the quarter clock phase. The  
MAX3620 is offered in a small 3mm x 3mm package  
which contains two delay lines of equal length that can  
be driven either differentially or single-endedly.  
Supports HSTL Source Terminated Lines  
All-Passive Design  
Compatible with 100Differential and 50Single-  
Ended Transmission Lines  
Small 3mm x 3mm Package  
Ordering Information  
Applications  
QDR/QDRII Memory Systems  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
6 TDFN  
Multiphase Clock Generation  
MAX3620AETT  
MAX3620BETT  
MAX3620CETT  
MAX3620DETT  
6 TDFN  
Pin Configuration  
6 TDFN  
6 TDFN  
TOP VIEW  
IN1  
COMMON  
IN2  
1
2
3
6
5
4
OUT1  
Selector Guide  
COMMON  
OUT2  
PART  
PKG CODE  
TOP MARK  
AJX  
MAX3620  
MAX3620AETT  
MAX3620BETT  
MAX3620CETT  
MAX3620DETT  
T633-2  
T633-2  
T633-2  
T633-2  
AIY  
AIZ  
*EP  
AJA  
TDFN  
*EP—EXPOSED PAD. MUST BE CONNECTED TO THE  
SAME POTENTIAL AS COMMON.  
Typical Application Circuit  
QDR II SRAM CLOCK OUTPUT  
HSTL SOURCE TERMINATED  
QDR II SRAM CLOCK INPUT  
HSTL HIGH-Z CMOS  
DELAY LINE  
1/4 CLOCK PERIOD  
50  
50Ω  
50Ω  
50Ω  
90° PHASE  
50Ω  
IN1  
OUT1  
COMMON  
IN2  
COMMON  
MAX3620  
270° PHASE  
50Ω  
OUT2  
180° PHASE  
50Ω  
0° PHASE  
50Ω  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  

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