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MAX13108E

更新时间： 2024-11-20 05:48:59
品牌 Logo 应用领域
美信 - MAXIM 转换器电平转换器
页数 文件大小 规格书
18页 168K
描述
16-Channel Buffered CMOS Logic-Level Translators

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中文翻译

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MAX13108E 数据手册

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19-3802; Rev 3; 6/08  
16-Channel Buffered CMOS  
Logic-Level Translators  
2/MAX3108E  
General Description  
Features  
The MAX13101E/MAX13102E/MAX13103E/MAX13108E  
16-bit bidirectional CMOS logic-level translators pro-  
vide the level shifting necessary to allow data transfer in  
multivoltage systems. These devices are inherently  
bidirectional due to their design and do not require the  
use of a direction input. Externally applied voltages,  
♦ Wide Supply Voltage Range  
Range of 1.65V to 5.5V  
V
CC  
V Range of 1.2V to V  
L
CC  
♦ ESD Protection on I/O V  
Lines  
CC  
15ꢀV ꢁuꢂan ꢃody ꢄodel  
♦ Up to 20ꢄbps Throughput  
V
and V , set the logic levels on either side of the  
L
CC  
devices. Logic signals present on the V side of the  
L
♦ Low 0.03µA Typical Quiescent Current  
♦ WLP and TQFN Pacꢀages  
device appear as a higher voltage logic signal on the  
V
CC  
side of the device, and vice-versa.  
Pin Configurations  
The MAX13101E/MAX13102E/MAX13103E feature an  
enable input (EN) that, when low, reduces the V  
and  
CC  
TOP VIEW OF BOTTOM LEADS  
V supply currents to less than 2µA. The MAX13108E  
L
features a multiplexing input (MULT) that selects one  
byte between the two, thus allowing multiplexing of the  
signals. The MAX13101E/MAX13102E/MAX13103E/  
30 29 28 27 26 25 24 23 22 21  
MAX13108E have 1ꢀ5V ESꢁ protection on the ꢂ/O V  
CC  
I/O V 13  
CC  
I/O V  
I/O V  
I/O V  
I/O V  
4
3
2
1
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
20  
19  
18  
17  
16  
15  
14  
13  
12  
CC  
CC  
CC  
CC  
side for greater protection in applications that route sig-  
nals externally. Three different output configurations are  
I/O V 14  
CC  
I/O V 15  
CC  
available during shutdown, allowing the ꢂ/O on the V  
CC  
side or the V side to be put in a high-impedance state  
L
I/O V 16  
CC  
or pulled to ground through an internal 65Ω resistor.  
MAX13101E  
MAX13102E  
MAX13103E  
V
V
CC  
CC  
The MAX13101E/MAX13102E/MAX13103E/MAX13108E  
V
L
V
L
accept V  
voltages from +1.6ꢀV to +ꢀ.ꢀV and V  
L
CC  
I/O V 1  
L
I/O V 16  
L
voltages from +1.2V to V , ma5ing them ideal for data  
CC  
I/O V 2  
L
I/O V 15  
L
*EP  
transfer between low-voltage ASꢂCs/PLꢁs and higher  
voltage systems. The MAX13101E/MAX13102E/  
MAX13103E/MAX13108E are available in 36-bump  
WLP and 40-pin TQFN pac5ages, and operate over the  
extended -40°C to +8ꢀ°C temperature range.  
I/O V 3  
L
I/O V 14  
L
+
I/O V 4  
L
I/O V 13  
L
11  
1
2
3
4
5
6
7
8
9
10  
Applications  
*EXPOSED PAD CONNECTED TO GROUND  
TQFN  
CMOS Logic-Level  
Translation  
PꢁAs  
Pin Configurations continued at end of data sheet.  
ꢁigital Still Cameras  
Smart Phones  
Portable Equipment  
Cell Phones  
Typical Operating Circuit appears at end of data sheet.  
Ordering Information/Selector Guide  
DATA  
I/O V STATE  
I/O V  
STATE  
ꢄULTIPLEXER  
FEATURE  
L
CC  
PART  
PIN-PACKAGE  
RATE (ꢄbps) DURING SꢁUTDOWN DURING SꢁUTDOWN  
36 WLP**  
3.06mm x 3.06mm  
ꢄAX13101EEWX+*  
MAX13101EETL+  
20  
High impedance  
65Ω to GNꢁ  
65Ω to GNꢁ  
No  
No  
40 TQFN-EP***  
ꢀmm x ꢀmm x 0.8mm  
20  
High impedance  
Note: All devices are specified over the -40°C to +8ꢀ°C operating temperature range.  
+ꢁenotes a lead-free/RoHS-compliant pac5age.  
*Future product—contact factory for availability.  
**WLP bumps are in a 6 x 6 array.  
***EP = Exposed pad.  
Ordering Inforꢂation/Selector Guide continued at end of data sheet.  
________________________________________________________________ ꢄaxiꢂ Integrated Products  
1
For pricing, delivery, and ordering inforꢂation, please contact ꢄaxiꢂ Direct at 1-888-629-4642,  
or visit ꢄaxiꢂ’s website at www.ꢂaxiꢂ-ic.coꢂ.  
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