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M74VHC1GT125DF1G PDF预览

M74VHC1GT125DF1G

更新时间: 2024-02-22 19:43:43
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器转换器电平转换器逻辑集成电路光电二极管PC
页数 文件大小 规格书
6页 89K
描述
Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs

M74VHC1GT125DF1G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOT-353
包装说明:TSSOP,针数:5
Reach Compliance Code:unknown风险等级:5.44
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:NOT SPECIFIED位数:1
功能数量:1端口数量:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):16 ns认证状态:COMMERCIAL
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1.25 mmBase Number Matches:1

M74VHC1GT125DF1G 数据手册

 浏览型号M74VHC1GT125DF1G的Datasheet PDF文件第2页浏览型号M74VHC1GT125DF1G的Datasheet PDF文件第3页浏览型号M74VHC1GT125DF1G的Datasheet PDF文件第4页浏览型号M74VHC1GT125DF1G的Datasheet PDF文件第5页浏览型号M74VHC1GT125DF1G的Datasheet PDF文件第6页 
MC74VHC1GT125  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHC1GT125 is a single gate noninverting buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
MARKING  
The MC74VHC1GT125 requires the 3−state control input (OE) to  
be set High to place the output into the high impedance state.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT125 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT125 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
DIAGRAMS  
5
5
W1 M G  
1
G
SC−88A/SOT−353/SC−70  
DF SUFFIX  
1
5
CASE 419A  
5
W1 M G  
G
1
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
1
V
CC  
= 0 V. These input and output structures help prevent device  
destruction caused by supply voltage − input/output voltage mismatch,  
battery backup, hot insertion, etc.  
CASE 483  
Features  
W1  
M
G
= Device Code  
= Date Code*  
= Pb−Free Package  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 62; Equivalent Gates = 16  
Pb−Free Packages are Available  
PIN ASSIGNMENT  
1
2
3
4
5
OE  
IN A  
GND  
OUT Y  
V
CC  
OE  
IN A  
GND  
V
CC  
5
4
1
2
FUNCTION TABLE  
OE Input  
OUT Y  
3
A Input  
Y Output  
L
H
X
L
L
L
H
Z
Figure 1. Pinout (Top View)  
H
OE  
IN A  
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 12  
MC74VHC1GT125/D  

M74VHC1GT125DF1G 替代型号

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