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Datasheet > M74HCT7259RM13TR
M74HCT7259RM13TR PDF预览

M74HCT7259RM13TR

更新时间： 2024-11-09 21:06:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
13页 310K
描述
HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16, SO-16

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中文翻译

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M74HCT7259RM13TR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.61其他特性：1:8 DMUX FOLLOWED BY LATCH
系列：HCTJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：D LATCH
最大I（ol）：0.08 A湿度敏感等级：3
位数：1功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：OPEN-DRAIN
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5 V
Prop。Delay @ Nom-Sup：45 ns传播延迟（tpd）：55 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：LOW LEVEL宽度：3.9 mm
Base Number Matches：1

M74HCT7259RM13TR 数据手册

 浏览型号M74HCT7259RM13TR的Datasheet PDF文件第2页浏览型号M74HCT7259RM13TR的Datasheet PDF文件第3页浏览型号M74HCT7259RM13TR的Datasheet PDF文件第4页浏览型号M74HCT7259RM13TR的Datasheet PDF文件第5页浏览型号M74HCT7259RM13TR的Datasheet PDF文件第6页浏览型号M74HCT7259RM13TR的Datasheet PDF文件第7页 
M74HCT7259  
8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER  
OPEN DRAIN, INVERTING OUTPUT  
■
■
■
LOW POWER DISSIPATION:  
I
=4µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
HIGH CURRENT OPEN DRAIN OUTPUT UP  
TO 80 mA  
DIP  
SOP  
TSSOP  
DESCRIPTION  
The M74HCT7259 is an high speed CMOS 8 BIT  
ADDRESSABLE LATCH/DECODER fabricated  
with silicon gate C MOS technology.  
ORDER CODES  
2
PACK.  
TUBE  
M74HCT7259B1R  
T & R  
This device has single data input (D) 8 LATCH  
inverted OUTPUTS (Q0 - Q7), 3 address inputs  
(A, B and C), common enable input (ENABLE)  
and a common CLEAR input. To operate this  
device as an addressable latch, data is held on the  
D input, and the address of the latch into which the  
data is to be entered is held on the A, B and C  
inputs.  
When ENABLE is taken low the data flows  
through to the address output. The data is stored  
on the positive going edge of the ENABLE pulse.  
All unaddressed latches will remain unaffected.  
With ENABLE in the high state the device is  
deselected and all latches remain in their previous  
state, unaffected by changes on the data or  
address inputs. To eliminate the possibility of  
entering erroneous data into the latches, the  
ENABLE should be held high (inactive) while the  
address lines are changing. If ENABLE is held  
DIP  
SOP  
M74HCT7259M1R M74HCT7259RM13TR  
M74HCT7259TTR  
TSSOP  
high and CLEAR is taken low all eight latches are  
cleared to the HIGH (OFF) state. If ENABLE is low  
all latches except the addressed latch will be  
cleared. The address latch will instead be the  
complement of the  
D
input, effectively  
implementing a 3 to 8 line decoder. Internal clamp  
diodes protect the open drain outputs against over  
voltages due to inductive loads.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
September 2001  
1/13  
1234567...13

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