Datasheet > M74HCT7259RM13TR

M74HCT7259RM13TR

更新时间： 2024-11-07 21:06:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		光电二极管输出元件逻辑集成电路触发器
页数	文件大小	规格书
13页	310K
描述
HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16, SO-16

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技术参数
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M74HCT7259RM13TR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.4	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.61	其他特性：	1:8 DMUX FOLLOWED BY LATCH
系列：	HCT	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4	长度：	9.9 mm
负载电容（CL）：	50 pF	逻辑集成电路类型：	D LATCH
最大I（ol）：	0.08 A	湿度敏感等级：	3
位数：	1	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	OPEN-DRAIN
输出极性：	INVERTED	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	5 V
Prop。Delay @ Nom-Sup：	45 ns	传播延迟（tpd）：	55 ns
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	FF/Latches	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
触发器类型：	LOW LEVEL	宽度：	3.9 mm
Base Number Matches：	1

M74HCT7259RM13TR 数据手册

M74HCT7259

8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER

OPEN DRAIN, INVERTING OUTPUT

■

LOW POWER DISSIPATION:

=4µA(MAX.) at T =25°C

COMPATIBLE WITH TTL OUTPUTS :

= 2V (MIN.) V = 0.8V (MAX)

HIGH CURRENT OPEN DRAIN OUTPUT UP

TO 80 mA

DIP

SOP

TSSOP

DESCRIPTION

The M74HCT7259 is an high speed CMOS 8 BIT

ADDRESSABLE LATCH/DECODER fabricated

with silicon gate C MOS technology.

ORDER CODES

PACK.

TUBE

M74HCT7259B1R

T & R

This device has single data input (D) 8 LATCH

inverted OUTPUTS (Q0 - Q7), 3 address inputs

(A, B and C), common enable input (ENABLE)

and a common CLEAR input. To operate this

device as an addressable latch, data is held on the

D input, and the address of the latch into which the

data is to be entered is held on the A, B and C

inputs.

When ENABLE is taken low the data flows

through to the address output. The data is stored

on the positive going edge of the ENABLE pulse.

All unaddressed latches will remain unaffected.

With ENABLE in the high state the device is

deselected and all latches remain in their previous

state, unaffected by changes on the data or

address inputs. To eliminate the possibility of

entering erroneous data into the latches, the

ENABLE should be held high (inactive) while the

address lines are changing. If ENABLE is held

DIP

SOP

M74HCT7259M1R M74HCT7259RM13TR

M74HCT7259TTR

TSSOP

high and CLEAR is taken low all eight latches are

cleared to the HIGH (OFF) state. If ENABLE is low

all latches except the addressed latch will be

cleared. The address latch will instead be the

complement of the

input, effectively

implementing a 3 to 8 line decoder. Internal clamp

diodes protect the open drain outputs against over

voltages due to inductive loads.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

September 2001

1/13

12 3 4 5 6 7...13

中文翻译

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与M74HCT7259RM13TR相关器件

型号	品牌	获取价格	描述	数据表
M74HCT7259TTR	STMICROELECTRONICS	获取价格	HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16, TSSOP-16
M74HCT74	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74-1	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74B1R	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74C1R	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74M1R	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74MTC	FAIRCHILD	获取价格	Dual D-Type Flip-Flop with Preset and Clear
M74HCT74MTCX	FAIRCHILD	获取价格	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
M74HCT74RM13TR	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74TTR	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

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