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M74HCT7259M1R PDF预览

M74HCT7259M1R

更新时间： 2024-11-06 22:17:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器触发器锁存器逻辑集成电路光电二极管输出元件双倍数据速率
页数 文件大小 规格书
11页 92K
描述
8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT

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中文翻译

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M74HCT7259M1R 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SO-16
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.61
Is Samacsys：N其他特性：1:8 DMUX FOLLOWED BY LATCH
系列：HCTJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：150 pF逻辑集成电路类型：D LATCH
最大I（ol）：0.08 A位数：1
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：OPEN-DRAIN输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5 V
Prop。Delay @ Nom-Sup：45 ns传播延迟（tpd）：55 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：LOW LEVEL
宽度：3.9 mmBase Number Matches：1

M74HCT7259M1R 数据手册

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M74HCT7259  
8BIT ADDRESSABLE LATCH/DECODER/RELAIS  
DRIVER (OPEN DRAIN,INVERTING OUTPUT)  
PRELIMINARY DATA  
■
■
■
■
LOW POWER DISSIPATION  
CC =4 µA (MAX.) AT TA =25 °C  
COMPATIBLEWITH TTL OUTPUTS  
VIH =2V (MIN) VIL =0.8V(MAX)AT 5V  
OUTPUT DRIVECAPABILITY  
90 LSTTL LOADS  
I
DIP  
SOP  
HIGH CURRENT OPENDRAIN OUTPUT UP  
TO80 mA  
ORDER CODES  
PACKAGE  
TUBE  
T & R  
The M74HCT7259 is a high speed CMOS 8 BIT  
ADDRESSABLE LATCH/DECODER fabricated in  
silicon gate C2MOS technology. It has the same  
high speed performance of LSTTL combined with  
true CMOS low power consumption.  
The M74HCT7259 has single data input (D) 8  
LATCH inverted OUTPUTS (Q0-Q7), 3 address  
inputs (A, B and C), common enable input  
(ENABLE) and a common CLEAR input. To  
operate this device as an addressablelatch, data  
is held on the D input, and the address of the  
latch into which the data is to be entered is held  
on the A, B and C inputs.  
When ENABLE is taken low the data flows  
through to the address output. The data is stored  
on the positive-going edge of the ENABLE pulse.  
All unadressed latches will remain unaffected.  
With ENABLE in the high state the device is  
deselected and all latches remain in their  
previous state, unaffected by changes on the  
DIP  
M74HCT7259B1R  
SOP  
M74HCT7259M1R M74HCT7259M1RTR  
data or address inputs. To eliminate the  
possibility of entering erroneous data into the  
latches, the ENABLE should be held high  
(inactive) while the address lines are changing. If  
ENABLE is held high and CLEAR is taken low all  
eight latches are cleared to the HIGH (OFF)  
state. If ENABLE is low all latches except the  
addressed latch will be cleared. The address  
latch will instead be the complement of the D  
input,effectively implementing a 3 to 8 line  
decoder. Internal clamp diodes protect the open  
drain outputs against over voltages due to  
inductiveloads.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/11  
February 2000  
1234567...11

中文翻译

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