Datasheet > M74HCT7259

M74HCT7259

更新时间： 2024-09-16 23:01:27

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器驱动器锁存器输出元件双倍数据速率
页数	文件大小	规格书
11页	92K
描述
8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT

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中文翻译

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M74HCT7259 数据手册

M74HCT7259

8BIT ADDRESSABLE LATCH/DECODER/RELAIS

DRIVER (OPEN DRAIN,INVERTING OUTPUT)

PRELIMINARY DATA

■

LOW POWER DISSIPATION

_CC=4 µA (MAX.) AT T_A=25 °C

COMPATIBLEWITH TTL OUTPUTS

V_IH=2V (MIN) V_IL=0.8V(MAX)AT 5V

OUTPUT DRIVECAPABILITY

90 LSTTL LOADS

DIP

SOP

HIGH CURRENT OPENDRAIN OUTPUT UP

TO80 mA

ORDER CODES

PACKAGE

TUBE

T & R

The M74HCT7259 is a high speed CMOS 8 BIT

ADDRESSABLE LATCH/DECODER fabricated in

silicon gate C2MOS technology. It has the same

high speed performance of LSTTL combined with

true CMOS low power consumption.

The M74HCT7259 has single data input (D) 8

LATCH inverted OUTPUTS (Q0-Q7), 3 address

inputs (A, B and C), common enable input

(ENABLE) and a common CLEAR input. To

operate this device as an addressablelatch, data

is held on the D input, and the address of the

latch into which the data is to be entered is held

on the A, B and C inputs.

When ENABLE is taken low the data flows

through to the address output. The data is stored

on the positive-going edge of the ENABLE pulse.

All unadressed latches will remain unaffected.

With ENABLE in the high state the device is

deselected and all latches remain in their

previous state, unaffected by changes on the

DIP

M74HCT7259B1R

SOP

M74HCT7259M1R M74HCT7259M1RTR

data or address inputs. To eliminate the

possibility of entering erroneous data into the

latches, the ENABLE should be held high

(inactive) while the address lines are changing. If

ENABLE is held high and CLEAR is taken low all

eight latches are cleared to the HIGH (OFF)

state. If ENABLE is low all latches except the

addressed latch will be cleared. The address

latch will instead be the complement of the D

input,effectively implementing a 3 to 8 line

decoder. Internal clamp diodes protect the open

drain outputs against over voltages due to

inductiveloads.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/11

February 2000

12 3 4 5 6 7...11

中文翻译

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与M74HCT7259相关器件

型号	品牌	获取价格	描述	数据表
M74HCT7259B1R	STMICROELECTRONICS	获取价格	8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT
M74HCT7259M1R	STMICROELECTRONICS	获取价格	8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT
M74HCT7259M1RTR	STMICROELECTRONICS	获取价格	8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT
M74HCT7259RM13TR	STMICROELECTRONICS	获取价格	HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16, SO-16
M74HCT7259TTR	STMICROELECTRONICS	获取价格	HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16, TSSOP-16
M74HCT74	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74-1	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74B1R	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74C1R	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
M74HCT74M1R	STMICROELECTRONICS	获取价格	DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

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