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M74HCT652TTR

更新时间： 2024-09-17 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
12页 201K
描述
HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, TSSOP-24

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中文翻译

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M74HCT652TTR 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.78Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：HCTJESD-30 代码：R-PDSO-G24
长度：7.8 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL电源：5 V
Prop。Delay @ Nom-Sup：55 ns传播延迟（tpd）：52 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
翻译：N/A触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

M74HCT652TTR 数据手册

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M74HCT651  
M74HCT652  
HCT651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)  
HCT652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)  
.
HIGH SPEED  
fMAX = 60 MHz (TYP.) AT VCC = 5V  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2 V (MIN.) AT VIL = 0.8V (MAX)  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX) AT TA = 25 oC  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 6 mA (mIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
.
.
.
.
.
.
B1R  
M1R  
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
M74HCXXXM1R  
M74HCXXXB1R  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS651/652  
DESCRIPTION  
M74HCT651/652 are high speed CMOS OCTAL  
PIN CONNECTIONS (top view)  
BUS  
TRANSCEIVERS  
AND  
REGISTERS  
(3-STATE), fabricated in silicon gate C2MOS  
technology. They have the same high speed  
performance of LSTTL combined with true CMOS  
low power consumption. These devices consist of  
bus transceiver circuits, D-type flip-flops, and control  
circuitry arranged for multiplexed transmission of  
data directly from the input bus or from the internal  
storage registers. Enable GAB and GBA are  
provided to control the transceiver functions. Select  
AB and Select BA control pins are provided to select  
whether real-time or stored data is transfered. A low  
input level selects real-time data, and a high selects  
stored data. Data on the A or B bus, or both, can be  
stored in the internal D flip-flops by low-to-high  
transitions at the appropriate clock pins (CLOCK AB  
or CLOCK BA) regardless of the select or enable  
control pins. When select AB and select BAarein the  
real-time transfer mode, it is also possible to store  
data without using the internal D-type flip-flops by  
simultaneously enabling GAB and GBA. In this  
configuration each output reinforces its input. Thus,  
when all other data sources to the two sets of bus  
linesareat high impedance, each set ofbus lines will  
remain at its last state. All inputs are equipped with  
protection circuits against static discharge and  
transient excess voltage.This integrated circuit has  
input and output characteristics that are fully  
compatible with 54/74 LSTTL logic families.  
M54/74HCT devices are designed to directly  
interface HSCMOS systems with TTL and NMOS  
components. They are also plug in replacements for  
LSTTL devices giving a reduction of power  
consumption.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
GAB, GAB, CAB,  
SAB, SBA, CBA  
A, B  
October 1993  
1/12  
1234567...12

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