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M74HCT652RM13TR PDF预览

M74HCT652RM13TR

更新时间: 2024-11-26 18:14:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
15页 330K
描述
HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, SOP-24

M74HCT652RM13TR 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:HCT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.006 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):250电源:5 V
Prop。Delay @ Nom-Sup:55 ns传播延迟(tpd):52 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

M74HCT652RM13TR 数据手册

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M74HCT652  
OCTAL BUS TRANSCEIVER/REGISTER  
WITH 3 STATE OUTPUTS  
HIGH SPEED:  
= 55 MHz (TYP.) at V = 4.5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 652  
TBE  
T & R  
DIP  
SOP  
MHCT652B1R  
M74HCT652M1R M74HCT652RM13TR  
M74HCT652TTR  
DESCRIPTION  
TSSOP  
The 74HCT652 is an advanced high-speed  
CMOS OCTAL BUS TRANSCEIVER AND  
REGISTER (3-STATE) fabricated with silicon gate  
BA) regardless of the select or enable control pins.  
When select AB and select BA are in the real time  
transfer mode, it is also possible to store data  
without using the internal D type flip-flops by  
simultaneously enabling GAB and GBA. In this  
configuration each output reinforces its input.  
Thus, when all other data sources to the two sets  
of bus lines are at high impedance, each set of  
bus lines will remain at its last state.  
2
C MOS technology.  
This device consists of bus transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
input bus or from the internal storage registers.  
Enable GAB and GBA are provided to control the  
transceiver functions. SelecB(SAB) and select  
BA(SBA) control pins e provided to select  
whether real-time stored data is transferred. A  
low input level selects real-time data, and a high  
selects stored data.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
Data on the A or B bus, or both, can be stored in  
the innal D flip-flops by low-to-high transition at  
the appropriate clock pins (CLOCK AB or CLOCK  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2003  
1/15  

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