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M74HCT648RM13TR PDF预览

M74HCT648RM13TR

更新时间: 2024-11-23 21:17:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
15页 408K
描述
HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, SOP-24

M74HCT648RM13TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:HCT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:60 ns
传播延迟(tpd):70 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

M74HCT648RM13TR 数据手册

 浏览型号M74HCT648RM13TR的Datasheet PDF文件第2页浏览型号M74HCT648RM13TR的Datasheet PDF文件第3页浏览型号M74HCT648RM13TR的Datasheet PDF文件第4页浏览型号M74HCT648RM13TR的Datasheet PDF文件第5页浏览型号M74HCT648RM13TR的Datasheet PDF文件第6页浏览型号M74HCT648RM13TR的Datasheet PDF文件第7页 
M74HCT648  
OCTAL BUS TRANSCEIVER/REGISTER  
WITH 3 STATE OUTPUTS (INVERTING)  
HIGH SPEED:  
= 60 MHz (TYP.) at V = 4.5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
DIP  
SOP  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
ORDER CODES  
PACKAGE  
IH  
IL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 648  
TUBE  
T & R  
DIP  
SOP  
M74HCT648B1R  
M74HCT648M1R M74HCT648RM13TR  
M74HCT648TTR  
DESCRIPTION  
TSSOP  
The 74HCT648 is an advanced high-speed  
CMOS OCTAL BUS TRANSCEIVER AND  
REGISTER (3-STATE) fabricated with silicon gate  
(transparent mode) data. The direction control  
determines which bus will receive data when  
enable G is active (low). In the isolation mode  
(enable G high), "A" data may be stored in one  
register and/or "B" data may be stored in the other  
register. When an output function is disabled, the  
input function is still enabled and may be used to  
store and transmit data. Only one of the two  
buses, A or B, may be driven at a time.  
2
C MOS technology.  
This device consists of bus transceiver circuits  
with 3 state, D-type flip-flops, and control circuitry  
arranged for multiplexed transmission of data  
directly from the input bus or from the internal  
registers. Data on the A or B bus will be clocked  
into register on the low to high transition of the  
appropriate clock pin (Clock AB or Clock BA).  
Enable (G) and direction (DIR) pins are provided  
to control the transceiver functions. In the  
transceiver mode, data present at the  
high-impedance port may be stored in either  
register or in both. The select controls (Select AB,  
Select BA) can multiplex stored and real time  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2003  
1/15  

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