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M74HCT125C1R PDF预览

M74HCT125C1R

更新时间: 2024-11-02 05:10:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
10页 254K
描述
QUAD BUS BUFFERS 3-STATE

M74HCT125C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:compliant
风险等级:5.83Is Samacsys:N
控制类型:ENABLE LOW系列:HCT
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.9662 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:1功能数量:4
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:26 ns
传播延迟(tpd):34 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.9662 mm
Base Number Matches:1

M74HCT125C1R 数据手册

 浏览型号M74HCT125C1R的Datasheet PDF文件第2页浏览型号M74HCT125C1R的Datasheet PDF文件第3页浏览型号M74HCT125C1R的Datasheet PDF文件第4页浏览型号M74HCT125C1R的Datasheet PDF文件第5页浏览型号M74HCT125C1R的Datasheet PDF文件第6页浏览型号M74HCT125C1R的Datasheet PDF文件第7页 
M54/74HCT125  
M54/74HCT126  
QUAD BUS BUFFERS (3-STATE)  
.
.
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.
.
.
.
HIGH SPEED  
tPD = 12 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT 25 °C  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS125/126  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXB1R  
M74HCTXXXM1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT125/126 are high speed CMOS  
QUAD BUS BUFFER (3-STATE) FABRICATED IN  
SILICON GATE C2MOS technology. They have the  
same high speed performance ofLSTTL combined  
with true CMOS low power consumption. These de-  
vices require the same 3-STATE control input G to  
be takenhigh to make the output go into the high im-  
pedance state.This integrated circuit has input and  
output characteristics that are fully compatible with  
54/74 LSTTL logic families. M54/74HCT devices  
are designed to directly interface HSC2MOS sys-  
tems with TTL and NMOS components. They are  
also plug in replacements for LSTTL devices giving  
a reduction of power consumption. All inputs are  
equipped with protection circuits against static dis-  
charge and transient excess voltage.  
PIN CONNECTIONS (top view)  
HCT125  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
HCT126  
NC =  
No Internal  
Connection  
October 1993  
1/10  

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