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M74HC623TTR PDF预览

M74HC623TTR

更新时间: 2024-11-08 05:00:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 317K
描述
OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (NON INVERTING)

M74HC623TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.73Is Samacsys:N
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G20
长度:6.5 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:26 ns传播延迟(tpd):195 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
翻译:N/A宽度:4.4 mm
Base Number Matches:1

M74HC623TTR 数据手册

 浏览型号M74HC623TTR的Datasheet PDF文件第2页浏览型号M74HC623TTR的Datasheet PDF文件第3页浏览型号M74HC623TTR的Datasheet PDF文件第4页浏览型号M74HC623TTR的Datasheet PDF文件第5页浏览型号M74HC623TTR的Datasheet PDF文件第6页浏览型号M74HC623TTR的Datasheet PDF文件第7页 
M74HC623  
OCTAL BUS TRANSCEIVER  
WITH 3 STATE OUTPUTS (NON INVERTING)  
HIGH SPEED:  
= 10ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC623B1R  
M74HC623M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 623  
M74HC623RM13TR  
M74HC623TTR  
TSSOP  
DESCRIPTION  
The 74HC623 is an advanced high-speed CMOS  
device  
the capability to store data by  
OCTAL  
BUS  
TRANSCEIVER  
(3-STATE)  
simultaneous enabling of GBA and GAB.  
Each output reinforces its input in this transceiver  
configuration. Thus, when both control inputs are  
enabled and all other data sources to the two sets  
of bus lines are at high impedance, both sets of  
bus lines (16 in all) will remain at their last states.  
The 8-bit codes appearing on the two sets of  
buses will be identical.  
fabricated with silicon gate technology.  
This IC is intended for two-way asynchronous  
communication between data buses. The control  
function  
implementation  
allows  
maximum  
flexibility in timing.  
This device allows data transmission from the A  
bus to B bus or from the B to the A bus depending  
upon the logic level levels at the enable inputs  
(GBA and GAB). The enable inputs can be used to  
disable the device so that the buses are effectively  
isolated. The dual enable configuration gives this  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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