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M74HC623C1R PDF预览

M74HC623C1R

更新时间: 2024-11-06 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
11页 261K
描述
OCTAL BUS TRANSCEIVER HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING

M74HC623C1R 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:21 ns
传播延迟(tpd):33 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:8.965 mmBase Number Matches:1

M74HC623C1R 数据手册

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M54/74HC620  
M54/74HC623  
OCTAL BUS TRANSCEIVER  
HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING  
.
HIGH SPEED  
tPD = 10 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
.
.
.
.
.
.
.
B1R  
F1R  
(Plastic Package)  
(Ceramic Package)  
M1R  
C1R  
(Micro Package)  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH LS620/623  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXM1R  
M74HCXXXB1R  
M74HCXXXC1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HC620/623 are high speed CMOS  
OCTAL BUS TRANSCEIVERS fabricated in silicon  
gate C2MOS technology. They have the same high  
speed performance of LSTTL combined with true  
CMOS low power consumption.  
These octal bus transceivers are designed for asyn-  
chronous two-way communication between data  
buses. The control function implementation allows  
maximum flexibility in timing.  
These devices allow data transmission from the A  
bus to B bus or from the B to the A bus depending  
upon the logic levels at the enable inputs (GBA and  
GAB). The enable inputs can be used to disable the  
device so that the buses are effectively isolated.  
The dual-enable configuration gives these devices  
the capability tostoredata by simultaneous enabling  
of GBA and GAB.  
Each output reinforces its input in this transceiver  
configuration. Thus, when both control inputs are  
enabled and all other data sources to the two sets  
of bus lines are at high impedance, both sets of bus  
lines (16 in all) will remain at their last states. The 8-  
bit codes appearing on the two sets of buses will be  
identical for the ’HC623 or complementary for the  
’HC620. All inputs are equipped with protection cir-  
cuits against static discharge and transient excess  
voltage.  
NC =  
No Internal  
Connection  
October 1992  
1/11  

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