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M74HC595RM13TR PDF预览

M74HC595RM13TR

更新时间: 2024-11-08 22:25:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器触发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
13页 284K
描述
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE

M74HC595RM13TR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.07
其他特性:PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:4800000 Hz湿度敏感等级:3
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:24 MHz
Base Number Matches:1

M74HC595RM13TR 数据手册

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M54HC595  
M74HC595  
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)  
.
.
.
.
HIGH SPEED  
fMAX = 55 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
B1R  
(Plastic Package)  
F1R  
15 LSTTL LOADS FOR QA TO QH  
10 LSTTL LOADS FOR QH’  
(Ceramic Package)  
.
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.) FOR QA TO QH  
|IOH| = IOL = 4 mA (MIN.) FOR QH’  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
.
.
.
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC595F1R  
M74HC595B1R  
M74HC595M1R  
M74HC595C1R  
WITH LSTTL 54/74LS595  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC595 is a high speed CMOS 8-BIT  
SHIFT REGISTERS/OUTPUT LATCHES (3-  
STATE) fabricated in silicon C2MOS technology. It  
has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
This device contains an 8-bit serial-in, parallel-out  
shift register that feeds an 8-bit D-type storage reg-  
ister. The storage register has 8 3-STATE outputs.  
Separate clocks are provided for both the shift reg-  
ister and the storage register.  
The shift register has a direct-overriding clear, serial  
input, and serial output (standard) pins for cascad-  
ing. Both the shift register and storage register use  
positive-edge triggered clocks. If both clocks are  
connected together, the shift register state will al-  
ways be one clock pulse ahead of the storage reg-  
ister.  
NC =  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
No Internal  
Connection  
April 1993  
1/13  

M74HC595RM13TR 替代型号

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