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M74HC574C1R PDF预览

M74HC574C1R

更新时间： 2024-11-22 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器触发器逻辑集成电路输出元件
页数 文件大小 规格书
13页 273K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC564 INVERTING - HC574 NON INVERTING

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中文翻译

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M74HC574C1R 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.78
其他特性：BROADSIDE VERSION OF 374系列：HC/UH
JESD-30 代码：S-PQCC-J20JESD-609代码：e3
长度：8.965 mm负载电容（CL）：150 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：25000000 Hz
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC20,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
传播延迟（tpd）：48 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：FF/Latches
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：8.965 mmBase Number Matches：1

M74HC574C1R 数据手册

 浏览型号M74HC574C1R的Datasheet PDF文件第2页浏览型号M74HC574C1R的Datasheet PDF文件第3页浏览型号M74HC574C1R的Datasheet PDF文件第4页浏览型号M74HC574C1R的Datasheet PDF文件第5页浏览型号M74HC574C1R的Datasheet PDF文件第6页浏览型号M74HC574C1R的Datasheet PDF文件第7页 
M54/74HC564  
M54/74HC574  
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT  
HC564 INVERTING - HC574 NON INVERTING  
.
.
.
.
.
.
.
.
HIGH SPEED  
MAX = 62 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
f
V
NIH = VNIL = 28% VCC (MIN)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS564/574  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC564 and M54HC574 are high speed  
CMOS OCTAL D-TYPEFLIP FLOP WITH3-STATE  
OUTPUTS fabricated with in silicon gate C2MOS  
technology. They have the same high speed per-  
formance of LSTTL combined with true CMOS low  
power comsuption. These8-bit D-type flip-flops are  
controlled by a clockinput(CK) and anouputenable  
input (OE). On thepositive transition of theclock, the  
Q outputs willbesetto thelogic statethatweresetup  
at the D inputs (HC574) or their complements  
(HC564).  
ance state. The output control does notaffect the in-  
ternal operation of flip-flops. That is, theold data can  
be retained or the new data can be entered even  
while the outputs are off. The application engineer  
has a choice of combination of inverting and non-in-  
verting outputs. The 3-state output configuration  
and the wide choice of outline make bus-organized  
systemssimple. Allinputs are equipped withprotec-  
tion circuits against static discharge and transient  
excess voltage.  
While the OE input is low, the eight outputs will be  
in a normal logic state (high or low logic level), and  
while high level, the outputs will be in a high imped-  
PIN CONNECTION (top view)  
March 1993  
1/13  
1234567...13

中文翻译

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M74HC590B1N STMICROELECTRONICS

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M74HC590F1 STMICROELECTRONICS

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