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M74HC51 PDF预览

M74HC51

更新时间: 2024-11-02 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
9页 237K
描述
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE

M74HC51 数据手册

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M54HC51  
M74HC51  
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE  
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HIGH SPEED  
tPD = 10 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS51  
ORDER CODES :  
M54HC51F1R  
M74HC51B1R  
M74HC51M1R  
M74HC51C1R  
DESCRIPTION  
The M54/74HC51 is a high speed CMOS DUAL 2  
WIDE-2 INPUT AND/OR INVERT GATE fabricated  
in silicon gate C2MOS technology. It has the same  
high speed performance of LSTTL combined with  
true CMOS low power consumption. It contains a 2-  
WIDE 2-INPUT AND-OR-INVERT GATE and a 2-  
WIDE 3-INPUT AND-OR-INVERT GATE.  
PIN CONNECTIONS (top view)  
The internal circuit is composed of 3 stages (2-  
INPUT) or 5 stages (3-INPUT) including buffered  
output, which gives high noise immunity and a  
stableoutput.Allinputs are equipped withprotection  
circuits against static discharge and transient ex-  
cess voltage.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/9  

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