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M74HC373TTR PDF预览

M74HC373TTR

更新时间: 2024-11-04 05:00:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 242K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

M74HC373TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:7.65
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:31 ns传播延迟(tpd):265 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

M74HC373TTR 数据手册

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M74HC373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:  
= 12ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
DIP  
SOP  
M74HC373B1R  
M74HC373M1R  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
M74HC373RM13TR  
M74HC373TTR  
TSSOP  
DESCRIPTION  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
level) and when OE is in high level the outputs will  
be in a high impedance state.  
The M74HC373 is an high speed CMOS OCTAL  
LATCH WITH 3-STATE OUTPUTS fabricated  
with sub-micron silicon gate C MOS technology.  
2
This 8-BIT D-Type latches is controlled by a latch  
enable input (LE) and output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input. When the LE is  
taken low, the Q outputs will be latched at the logic  
level of D input data.  
The 3-State output configuration and the wide  
choice of outline make bus organized system  
simple.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

M74HC373TTR 替代型号

型号 品牌 替代类型 描述 数据表
MM74HC373MTCX FAIRCHILD

完全替代

暂无描述
MC74HC373ADTR2G ONSEMI

类似代替

Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon&#

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