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M74HC323F1R PDF预览

M74HC323F1R

更新时间: 2024-09-29 22:10:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
15页 307K
描述
HC323 8BITPIPOSHIFTREGISTERWITHSYNCHRONOUS CLEAR HC299 8BITPIPOSHIFTREGISTERWITHASYNCHRONOUS CLEAR

M74HC323F1R 数据手册

 浏览型号M74HC323F1R的Datasheet PDF文件第2页浏览型号M74HC323F1R的Datasheet PDF文件第3页浏览型号M74HC323F1R的Datasheet PDF文件第4页浏览型号M74HC323F1R的Datasheet PDF文件第5页浏览型号M74HC323F1R的Datasheet PDF文件第6页浏览型号M74HC323F1R的Datasheet PDF文件第7页 
M54/74HC299  
M54/74HC323  
HC299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR  
HC323 8 BIT PIPO SHIFT REGISTER WITH SYNCHRONOUS CLEAR  
.
HIGH SPEED  
fMAX = 42 MHz (TYP.) AT VCC = 5V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS FOR QA’ TO QH’  
15 LSTTL LOADS FOR QA TO QH  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 6 mA (MIN.) FOR QA, TO QH,  
IOH = IOL = 4 mA (MIN.) FOR QA, TO QH  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
.
.
.
B1R  
F1R  
(Plastic Package)  
(Ceramic Package)  
.
.
.
.
M1R  
C1R  
(Micro Package)  
(Chip Carrier)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXM1R  
M74HCXXXB1R  
M74HCXXXC1R  
WITH 54/74LS299  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC299/323 are high speed CMOS 8-  
BIT PIPO SHIFT REGISTERS (3-STATE) fabri-  
cated with silicon gate C2MOS technology.  
They achieve the high speed operation similar to  
equivalent LSTTL while maintaining the CMOS low  
power consumption.  
These devices have four modes (HOLD, SHIFT  
LEFT,SHIFT RIGHTand LOADDATA). Each mode  
is chosen by two function select inputs (S0, S1).  
When one or both enable inputs, (G1, G2) are high,  
the eight input/output terminals are in the high-  
impedance state ; however sequential operation or  
clearing of the register is not affected.  
Clear function on the HC299 is asynchronous to  
CLOCK, while the HC323 is cleared synchronous to  
clock.  
NC =  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
No Internal  
Connection  
October 1993  
1/15  

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