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M74HC109C1R PDF预览

M74HC109C1R

更新时间: 2024-02-22 22:06:16
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路
页数 文件大小 规格书
11页 251K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC109C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:N系列:HC/UH
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.9662 mm负载电容(CL):50 pF
逻辑集成电路类型:J-KBAR FLIP-FLOP最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.004 A位数:2
功能数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):38 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.9662 mm最小 fmax:25 MHz
Base Number Matches:1

M74HC109C1R 数据手册

 浏览型号M74HC109C1R的Datasheet PDF文件第2页浏览型号M74HC109C1R的Datasheet PDF文件第3页浏览型号M74HC109C1R的Datasheet PDF文件第4页浏览型号M74HC109C1R的Datasheet PDF文件第5页浏览型号M74HC109C1R的Datasheet PDF文件第6页浏览型号M74HC109C1R的Datasheet PDF文件第7页 
M54HC109  
M74HC109  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
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HIGH SPEED  
MAX = 63 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
CC = 2 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
NIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS109  
f
I
V
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC109F1R  
M74HC109B1R  
M74HC109M1R  
M74HC109C1R  
DESCRIPTION  
The M54/74HC109 is a high speed CMOS DUAL J-  
K FLIP-FLOP WITH PRESET AND CLEAR fabri-  
cated in silicon gate C2MOS technology.  
PIN CONNECTIONS (top view)  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
In accordance with the logic level on the J and K  
input is device changes state on positive going tran-  
sitions of the clock pulse. CLEAR and PRESET are  
independent of the clock and accomplished bya low  
logic level on the corresponding input.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/11  

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