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M74HC109_01 PDF预览

M74HC109_01

更新时间: 2024-01-09 02:31:16
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
12页 188K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC109_01 数据手册

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M74HC109  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 67MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC109B1R  
M74HC109M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 109  
M74HC109RM13TR  
M74HC109TTR  
TSSOP  
DESCRIPTION  
are independent of the clock and are  
accomplished by a logic low on the corresponding  
input.  
The M74HC109 is an high speed CMOS DUAL  
J-K FLIP FLOP WITH PRESET AND CLEAR  
fabricated with silicon gate C MOS technology. In  
2
accordance with the logic level on the J and K  
input this device changes state on positive going  
transition of the clock pulse. CLEAR and PRESET  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

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