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M74HC107RM13TR PDF预览

M74HC107RM13TR

更新时间: 2024-09-29 21:11:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 159K
描述
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, SO-14

M74HC107RM13TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.27系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:21000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:2功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:NEGATIVE EDGE
宽度:3.9 mm最小 fmax:25 MHz
Base Number Matches:1

M74HC107RM13TR 数据手册

 浏览型号M74HC107RM13TR的Datasheet PDF文件第2页浏览型号M74HC107RM13TR的Datasheet PDF文件第3页浏览型号M74HC107RM13TR的Datasheet PDF文件第4页浏览型号M74HC107RM13TR的Datasheet PDF文件第5页浏览型号M74HC107RM13TR的Datasheet PDF文件第6页浏览型号M74HC107RM13TR的Datasheet PDF文件第7页 
M74HC107  
DUAL J-K FLIP FLOP WITH CLEAR  
HIGH SPEED :  
= 80MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC107B1R  
M74HC107M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 107  
M74HC107RM13TR  
M74HC107TTR  
TSSOP  
DESCRIPTION  
CLEAR input and Q and Q outputs. CLEAR is  
independent of the clock and accomplished by a  
logic low on the input.  
The M74HC107 is an high speed CMOS DUAL  
J-K FLIP FLOP fabricated with silicon gate  
C MOS technology. These flip-flop are edge  
2
sensitive to the clock input and change state on  
the negative going transition of the clock pulse.  
Each one has independent J, K, CLOCK, and  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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