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M68Z128N PDF预览

M68Z128N

更新时间: 2024-11-25 22:19:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器
页数 文件大小 规格书
12页 97K
描述
5V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

M68Z128N 数据手册

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M68Z128  
5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable  
ULTRA LOW DATA RETENTION CURRENT  
– 10nA (typical)  
– 2.0µA (max)  
OPERATION VOLTAGE: 5V ±10%  
128Kb x 8 VERY FAST SRAM with OUTPUT  
ENABLE  
EQUAL CYCLE and ACCESS TIMES: 55ns  
LOW V  
DATA RETENTION: 2V  
CC  
TRI-STATE COMMON I/O  
TSOP32 (N)  
8 x 20mm  
LOW ACTIVE and STANDBY POWER  
AUTOMATIC POWER-DOWN WHEN  
DESELECTED  
INTENDED FOR USE WITH ST  
®
®
ZEROPOWER AND TIMEKEEPER  
Figure 1. Logic Diagram  
CONTROLLERS  
DESCRIPTION  
The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS  
SRAM, organized as 131,072 words by 8 bits. The  
device features fully static operation requiring no  
external clocks or timing strobes, with equal ad-  
dress access and cycle times. It requires a single  
5V ±10% supply, and all inputs and outputs are  
TTL compatible.  
V
CC  
17  
8
A0-A16  
DQ0-DQ7  
Table 1. Signal Names  
W
E1  
E2  
G
A0-A16  
Address Inputs  
Data Input/Output  
Chip Enable 1  
Chip Enable 2  
Output Enable  
Write Enable  
M68Z128  
DQ0-DQ7  
E1  
E2  
G
W
V
SS  
AI00647  
V
Supply Voltage  
Ground  
CC  
V
SS  
NC  
Not Connected Internally  
March 2000  
1/12  

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