MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This system is an NTSC system PinP system that accommodates
subscreen composite input and main screen Y/C input. It is a
semiconductor IC circuit having a built-in 96K bit field memory and
an analog circuit, which permits a low-cost and compact system
configuration.
AVss3 (vcxo)
VCXO out
VCXO in
FILTER
1
2
52 AVssf (ana)
51
50
49
Cin
3
TESTEN
Yin
4
FEATURES
BIAS
5
TEST9
Y-PIP
48
47
• Built-in field memory 96K bit for PIP
• Built-in luminance signal vertical filter
AVdd3 (vcxo)
AVdd2 (m)
Vin (m)
6
7
46 TEST8
• No. of subscreen displays: 1 (two sizes, 1/9 and 1/16, can be
8
45
44
43
C-PIP
selected from.)
• No. of subscreen samples (1/9 - 1/16 sizes)
No. of quantization bits: 6 for all Y, B-Y and R-Y
No. of horizontal picture elements: 171(Y), 28.5 (B-Y, R-Y)
No. of vertical lines: 69/52
Vrt (m)
9
AVdd4 (da)
C-PIPin
Vrb (m)
10
AVss2 (m) 11
42 AVss4 (da)
41 Y-PIPin
• Subscreen frame display ON/OFF
AVdd1 (s)
Vin (s)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
• Built-in analog circuits such as sync chip clamp, VCXO, and ana-
40
ADJ-Ysub
log switch
• Built-in 2 channels of 8 bit A/D converter
Vrt (s)
39
38
37
36
35
34
33
Yout-sub
(for main signal burst lock and PIP sub signal)
Vrb (s)
ADJ-Csub
• Built-in two channels of 8 bit D/A converter (luminance and
chroma signals)
AVss1 (s)
RESET
Cout-sub
• I2C bus control
DVss3 (ram)
DVdd3 (ram)
SWMG/TEST7
VD/CSYNC/TEST6
Controls: display ON/OFF, display size selection, setting of
display position, frame ON/OFF, setting of frame level, selection
of frame animation/field still image, setting of Y delay amount,
color level, tint, black level, etc.
DVss1
DVdd1
BGP(s)/TEST0
SCK
APPLICATION
TV
32 HD/TEST5
CSYNC(s)/TEST1
ACK
31
30
29
28
27
SWM/TEST4
MCK
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-10 to 75°C
Input voltage (CMOS interface) "H"........................VDD×0.7 to VDD V
"L".............................0 to VDD×0.3V
DATA
fsc/TEST3
BGP(m)/TEST2
DVdd2
CLK
DVss2 26
Outline 52P4B
Output current (output buffer)........................................±4mA (MAX)
1
Output load capacitance............................................20pF (MAX)
Circuit current.........................................................................140mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
1 : Include pin capacitance (7pF)
1