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M5M5V5636GP-16 PDF预览

M5M5V5636GP-16

更新时间: 2024-09-23 22:18:59
品牌 Logo 应用领域
三菱 - MITSUBISHI 内存集成电路静态存储器时钟
页数 文件大小 规格书
17页 263K
描述
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

M5M5V5636GP-16 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFP包装说明:LQFP, QFP100,.63X.87
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.68最长访问时间:3.8 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):167 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:18874368 bit内存集成电路类型:STANDARD SRAM
内存宽度:36功能数量:1
端子数量:100字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.03 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.38 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

M5M5V5636GP-16 数据手册

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MITSUBISHI LSIs  
2001.July Rev.0.1  
Advanced Information  
Some parametric limits are subject to change.  
M5M5V5636GP –16  
Notice: This is not final specification.  
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM  
DESCRIPTION  
APPLICATION  
The M5M5V5636GP is a family of 18M bit synchronous SRAMs  
organized as 524288-words by 36-bit. It is designed to eliminate  
dead bus cycles when turning the bus around between reads and  
writes, or writes and reads. Mitsubishi's SRAMs are fabricated  
with high performance, low power CMOS technology, providing  
greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V  
I/O supply or a single 3.3V power supply and are 3.3V CMOS  
compatible.  
High-end networking products that require high bandwidth, such  
as switches and routers.  
FUNCTION  
Synchronous circuitry allows for precise cycle control  
triggered by a positive edge clock transition.  
Synchronous signals include : all Addresses, all Data Inputs, all  
Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),  
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,  
BWd#) and Read/Write (W#). Write operations are controlled by  
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)  
inputs. All writes are conducted with on-chip synchronous self-  
timed write circuitry.  
FEATURES  
• Fully registered inputs and outputs for pipelined operation  
• Fast clock speed: 167 MHz  
Asynchronous inputs include Output Enable (G#), Clock (CLK)  
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the  
SRAM in the power-down state.The Linear Burst order (LBO#) is  
DC operated pin. LBO# pin will allow the choice of either an  
interleaved burst, or a linear burst.  
All read, write and deselect cycles are initiated by the ADV  
LOW input. Subsequent burst address can be internally  
generated as controlled by the ADV HIGH input.  
• Fast access time: 3.8 ns  
• Single 3.3V -5% and +5% power supply VDD  
• Separate VDDQ for 3.3V or 2.5V I/O  
Individual byte write (BWa# - BWd#) controls may be tied  
LOW  
• Single Read/Write control pin (W#)  
• CKE# pin to enable clock and suspend operations  
• Internally self-timed, registers outputs eliminate the need to  
control G#  
• Snooze mode (ZZ) for power down  
• Linear or Interleaved Burst Modes  
• Three chip enables for simple depth expansion  
Package  
100pin TQFP  
PART NAME TABLE  
Active Current  
(max.)  
Standby Current  
(max.)  
Part Name  
Frequency  
167MHz  
Access  
3.8ns  
Cycle  
6.0ns  
M5M5V5636GP - 16  
340mA  
20mA  
1
Advanced Information  
M5M5V5636GP REV.0.1  
MITSUBISHI  
ELECTRIC  

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