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M5M5V5636GP-16 PDF预览

M5M5V5636GP-16

更新时间: 2024-01-01 06:46:08
品牌 Logo 应用领域
瑞萨 - RENESAS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 691K
描述
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

M5M5V5636GP-16 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.52
最长访问时间:3.8 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G100长度:20 mm
内存密度:18874368 bit内存集成电路类型:STANDARD SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX36
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

M5M5V5636GP-16 数据手册

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Renesas LSIs  
M5M5V5636GP –16  
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM  
PACKAGE  
DESCRIPTION  
100pin TQFP  
The M5M5V5636GP is a family of 18M bit synchronous  
SRAMs organized as 524288-words by 36-bit. It is designed to  
eliminate dead bus cycles when turning the bus around between  
reads and writes, or writes and reads. Renesas's SRAMs are  
fabricated with high performance, low power CMOS technology,  
providing greater reliability. M5M5V5636GP operates on 3.3V  
power/ 2.5V I/O supply or a single 3.3V power supply and are  
3.3V CMOS compatible.  
The M5M5V5636GP also operates on a single 2.5V power  
supply and is also 2.5V CMOS compatible. Therefore the  
M5M5V5636GP can replace the M5M5T5636GP.  
The M5M5V5636GP-16 operates at 167MHz or 133MHz and  
is guaranteed both AC DC electrical characteristics of 167MHz  
and those of 133MHz.  
APPLICATION  
High-end networking products that require high bandwidth, such  
as switches and routers.  
FUNCTION  
Synchronous circuitry allows for precise cycle control  
triggered by a positive edge clock transition.  
Synchronous signals include : all Addresses, all Data Inputs,  
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),  
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,  
BWd#) and Read/Write (W#). Write operations are controlled by  
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)  
inputs. All writes are conducted with on-chip synchronous  
self-timed write circuitry.  
Asynchronous inputs include Output Enable (G#), Clock (CLK)  
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the  
SRAM in the power-down state.The Linear Burst order (LBO#) is  
DC operated pin. LBO# pin will allow the choice of either an  
interleaved burst, or a linear burst.  
FEATURES  
• Fully registered inputs and outputs for pipelined operation  
• Fast clock speed: 167 MHz and 133MHz  
• Fast access time: 3.8 ns and 4.2ns  
All read, write and deselect cycles are initiated by the ADV  
LOW input. Subsequent burst address can be internally  
generated as controlled by the ADV HIGH input.  
• Single 3.3V -5% and +5% power supply VDD  
• Separate VDDQ for 3.3V or 2.5V I/O  
• Single 2.5V -5% and +5% power supply VDD  
• Individual byte write (BWa# - BWd#) controls may be tied  
LOW  
• Single Read/Write control pin (W#)  
• CKE# pin to enable clock and suspend operations  
• Internally self-timed, registers outputs eliminate the need  
to control G#  
• Snooze mode (ZZ) for power down  
• Linear or Interleaved Burst Modes  
• Three chip enables for simple depth expansion  
PART NAME  
M5M5V5636GP-16  
Active Current  
(max.)  
Standby Current  
(max.)  
Operate frequency  
167MHz  
Access  
3.8ns  
4.2ns  
Cycle  
6.0ns  
7.5ns  
380mA  
350mA  
30mA  
30mA  
133MHz  
1/18  
M5M5V5636GP-16 REV.2.0  

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