M5M5V4R04J-15

更新时间： 2024-09-23 22:06:31

品牌	Logo	应用领域
三菱 - MITSUBISHI		/
页数	文件大小	规格书
6页	59K
描述
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM

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数据手册

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M5M5V4R04J-15 数据手册

MITSUBISHI LSIs

M5M5V4R04J-12,-15

1997.11.20 Rev.F

4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM

DESCRIPTION

The M5M5V4R04J is a family of 1048576-word by 4-bit static

RAMs, fabricated with the high performance CMOS silicon gate

process and designed for high speed application.

The M5M5V4R04J is offered in a 32-pin plastic small outline J-

lead package(SOJ).

PIN CONFIGURATION (TOP VIEW)

32 A19

A¹⁸

A17

address

inputs

address

inputs

A¹⁶

A¹⁵

These device operate on a single 3.3V supply, and are directly

TTL compatible. They include a power down feature as well.

FEATURES

chip select

input

output enable

input

DQ1

VCC

GND

DQ2

data inputs/

outputs

DQ4 data inputs/

GND

VCC

outputs

(3.3V)

(0V)

• Fast access time

M5M5V4R04J-12 •••• 12ns(max)

M5M5V4R04J-15 •••• 15ns(max)

(0V)

(3.3V)

data inputs/

²³DQ3

outputs

• Low power dissipation

Active •••••••••• 297mW(typ)

Stand by ••••••• 3.3mW(typ)

outputs

A14

A¹³

write control

input

• Single +3.3V power supply

• Fully static operation : No clocks, No refresh

• Common data I/O

address

inputs

²⁰A12

address

inputs

A11

18 A10

• Easy memory expansion by S

A⁹

• Three-state outputs : OR-tie capability

• OE prevents data contention in the I/O bus

• Directly TTL compatible : All inputs and outputs

Outline 32P0K(SOJ)

APPLICATION

High-speed memory units

PACKAGE

32pin 400mil SOJ

BLOCK DIAGRAM

DQ1

DQ2

DQ3

DQ4

MEMORY ARRAY

512 ROWS

8192 COLUMNS

A⁵

address

inputs

data

inputs/

outputs

COLUMN I/O CIRCUITS

COLUMN ADDRESS

COLUMN

DECODERS

ADDRESS

VCC(3.3V)

GND(0V)

DECODERS

COLUMN INPUT BUFFERS

OE 27

16 18 19

31 32

20 21 22 28 29 30

_{A9 A10 A11A12 A13A14 A15 A16 A17 A18}A19

address

inputs

MITSUBISHI

ELECTRIC

12 3 4 5 6

中文翻译

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