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M5M4V16169DTP

更新时间： 2024-11-25 22:25:55
品牌 Logo 应用领域
三菱 - MITSUBISHI 静态存储器动态存储器
页数 文件大小 规格书
64页 733K
描述
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

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M5M4V16169DTP 数据手册

 浏览型号M5M4V16169DTP的Datasheet PDF文件第2页浏览型号M5M4V16169DTP的Datasheet PDF文件第3页浏览型号M5M4V16169DTP的Datasheet PDF文件第4页浏览型号M5M4V16169DTP的Datasheet PDF文件第5页浏览型号M5M4V16169DTP的Datasheet PDF文件第6页浏览型号M5M4V16169DTP的Datasheet PDF文件第7页 
MITSUBISHI LSIs  
M5M4V16169DTP/RT-7,-8,-10,-15  
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM  
Preliminary  
This document is a preliminary Target Spec. and some of the contents are subject to change without notice.  
PINCONFIGURATION  
DESCRIPTION  
(TOP VIEW)  
Vss  
Ad9  
Ad8  
Ad7  
Ad11  
Ad10  
As9  
As8  
As7  
As6  
DQ15  
Vss  
DQ14  
DQ13  
VccQ  
DQ12  
Vcc  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
1
2
3
4
5
6
7
8
9
Vcc  
DQCl  
DQCu  
CC1#  
CC0#  
The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input  
1.  
registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word  
by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single  
monolithic circuit. The block data transfer between the DRAM and the data  
transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a  
fundamental advantage over a conventional DRAM/SRAM cache.  
The RAM is fabricated with a high performance CMOS process, and is ideal for  
large-capacity memory systems where high speed, low power dissipation, and  
low cost are essential. The use of quadruple-layer polysilicon process combined  
with silicide and double layer aluminum wiring technology, a single-transistor  
dynamic storage stacked capacitor cell, and a six-transistor static storage cache  
cell provide high circuit density at reduced costs.  
WE#  
CS#  
CMd#  
CMs#  
K
DQ0  
Vss  
DQ1  
DQ2  
VddQ  
DQ3  
10  
11  
12  
13  
14  
15  
16  
17  
2.  
400 mil  
70Pin  
TSOP  
Type II  
Vss  
DQ4  
VccQ  
DQ5  
DQ6  
Vss  
DQ11  
VccQ  
DQ10  
DQ9  
Vss  
DQ8  
MCH  
G#  
As5  
As4  
As3  
Ad6  
Ad5  
Ad4  
Ad3  
ADF#  
Vss  
19  
20  
21  
22  
23  
24  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
0.65mm  
Lead  
Pitch  
FEATURES  
DQ7  
MCL 25  
SRAM  
Access/cycle  
DRAM  
Access/cycle  
Power  
Dissipation (Typ)  
Type name  
As0  
As1  
As2  
RAS#  
CAS#  
DTD#  
Ad0  
Ad1  
Ad2  
Vcc  
26  
27  
28  
DRAM: 530  
SRAM: 860  
29  
5.6ns/7ns  
6.4ns/8ns  
8.0ns/10ns  
8.0ns/15ns  
M5M4V16169TP/RT-7  
M5M4V16169TP/RT-8  
49ns/70ns  
56ns/80ns  
30  
31  
DRAM: 500  
SRAM: 800  
32  
33  
34  
DRAM: 430  
SRAM: 660  
DRAM: 330  
SRAM: 420  
M5M4V16169TP/RT-10  
M5M4V16169TP/RT-15  
60ns/90ns  
35  
Package code:70P3S-L  
75ns/120ns  
Vss  
Ad9  
Ad8  
Ad7  
Ad11  
Ad10  
As9  
As8  
As7  
As6  
DQ15  
Vss  
DQ14  
DQ13  
VccQ  
DQ12  
Vcc  
70  
1
2
3
4
5
6
7
DQCl  
DQCu  
CC1#  
CC0#  
WE#  
CS#  
CMd#  
CMs#  
K
DQ0  
Vss  
DQ1  
DQ2  
69  
# 70-pin,400-mil TSOP (type II ) with 0.65mm  
lead pitch and 23.49mm package length.  
68  
67  
66  
# Multiplexed DRAM address inputs for reduced pin  
count and higher system densities.  
# Selectable output operation (transparent / latched /  
registered) using set command register cycle.  
# Single 3.3V +/- 0.3V Power Supply.  
(3.3V +/- 0.15V for -7 part)  
# 2048 refresh cycles every 64ms (Ad0->Ad10).  
# Programmable burst length (1,2,4,8) and burst  
sequence (sequential,interleave) with no latency.  
# Synchronous design for precise control with  
an external clock (K).  
# Output retention by advanced mask clock (CMs#).  
# All inputs/outputs low capacitance and LVTTL  
compatible.  
# Separate DRAM and SRAM address inputs  
for fast SRAM access.  
65  
: Master Clock  
: Chip Select  
K
CS#  
64  
63  
8
: DRAM Clock Mask  
: Row Addr. Strobe  
: Column Addr. Strobe  
: Data Transfer Direction  
: DRAM Address  
: SRAM Clock Mask  
: Control Clocks  
CMd#  
RAS#  
CAS#  
DTD#  
Ad  
CMs#  
CC0#,CC1#  
WE#  
DQC(u/l)  
As  
G#  
DQ  
Vcc  
VccQ  
Vss  
62  
9
61  
10  
11  
12  
60  
59  
58  
13  
14  
15  
16  
17  
57  
400 mil  
70Pin  
TSOP  
Type II  
VccQ  
DQ3  
Vss  
56  
: Write Enable  
55  
Vcc  
: I/O Byte Control  
: SRAM Address  
: Output Enable  
: Data I/O  
: Power Supply  
: DQ Power Supply  
: Ground  
:Address Fetch clock  
This pin can be None-Connect.  
:Must Connect Low  
:Must Connect High  
54  
DQ4  
VccQ  
DQ5  
DQ6  
Vss  
DQ7  
MCL  
As0  
As1  
As2  
RAS#  
CAS#  
DTD#  
Ad0  
52  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
DQ11  
VccQ  
51  
0.65mm  
Lead  
Pitch  
DQ10 50  
49  
DQ9  
Vss 48  
47  
DQ8  
MCH  
ADF#  
46  
G# 45  
MCL  
MCH  
44  
As5  
As4 43  
42  
As3  
Ad6  
Ad5  
Ad4  
Ad3  
ADF#  
Vss  
41  
# Page Mode capability.  
# Auto Refresh capability.  
# Self Refresh capability.  
40  
39  
Ad1  
Ad2  
Vcc  
38  
37  
36  
Package code:70P3S-M  
1
MITSUBISHI ELECTRIC  
(REV 1.0) Jul. 1998  
1234567...64

中文翻译

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与M5M4V16169DTP相关器件

型号 品牌 获取价格 描述 数据表
M5M4V16169DTP-10 MITSUBISHI

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 		16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-15 MITSUBISHI

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 		16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-7 MITSUBISHI

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 		16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-8 MITSUBISHI

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 		16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169TP-12 MITSUBISHI

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 		Cache DRAM, 1MX16, 56ns, CMOS, PDSO68, 0.400 INCH, 0.65 MM PITCH, TSOP2-70/68
M5M4V16169TP-12T MITSUBISHI

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 		Cache DRAM, 1MX16, CMOS, PDSO68, 0.400 INCH, 0.65 MM PITCH, PLASTIC, TSOP2-70/68
M5M4V16169TP-15T MITSUBISHI

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 		Cache DRAM, 1MX16, CMOS, PDSO68, 0.400 INCH, 0.65 MM PITCH, PLASTIC, TSOP2-70/68
M5M4V16169TP-20T MITSUBISHI

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 		Cache DRAM, 1MX16, CMOS, PDSO68, 0.400 INCH, 0.65 MM PITCH, PLASTIC, TSOP2-70/68
M5M4V16400CJ-5 MITSUBISHI

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 		Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOJ-26/24
M5M4V16400CJ-5S MITSUBISHI

获取价格

 		Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOJ-26/24

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