5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> M5LV-128/104-12AI
M5LV-128/104-12AI PDF预览

M5LV-128/104-12AI

更新时间： 2024-11-23 23:13:51
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
47页 1092K
描述
Fifth Generation MACH Architecture

阅读下载

中文翻译

获取价格

M5LV-128/104-12AI 数据手册

 浏览型号M5LV-128/104-12AI的Datasheet PDF文件第2页浏览型号M5LV-128/104-12AI的Datasheet PDF文件第3页浏览型号M5LV-128/104-12AI的Datasheet PDF文件第4页浏览型号M5LV-128/104-12AI的Datasheet PDF文件第5页浏览型号M5LV-128/104-12AI的Datasheet PDF文件第6页浏览型号M5LV-128/104-12AI的Datasheet PDF文件第7页 
MACH 5 CPLD Family  
Fifth Generation MACH Architecture  
FEATURES  
  High logic densities and I/Os for increased logic integration  
— 128 to 512 macrocell densities  
— 68 to 256 I/Os  
  Wide selection of density and I/O combinations to support most application needs  
— 6 macrocell density options  
— 7 I/O options  
— Up to 4 I/O options per macrocell density  
— Up to 5 density & I/O options for each package  
  Performance features to fit system needs  
— 5.5 ns t Commercial, 7.5 ns t Industrial  
PD  
PD  
— 182 MHz f  
CNT  
— Four programmable power/speed settings per block  
  Flexible architecture facilitates logic design  
— Multiple levels of switch matrices allow for performance-based routing  
— 100% routability and pin-out retention  
— Synchronous and asynchronous clocking, including dual-edge clocking  
— Asynchronous product- or sum-term set or reset  
— 16 to 64 output enables  
— Functions of up to 32 product terms  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— IEEE 1149.1 compliant for boundary scan testing  
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port  
— PCI compliant (-5/-6/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system design  
— Bus-Friendly™ Inputs & I/Os  
— Individual output slew rate control  
— Hot socketing  
— Programmable security bit  
2
  Advanced E CMOS process provides high performance, cost effective solutions  
  Supported by ispDesignEXPERT™ softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for MACH 5 devices  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice and Third-party hardw are programming support  
— LatticePRO™ software for in-system programmability support on PCs and Automated Test  
Equipment  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# 20446  
Amendment/0  
Rev: I  
Issue Date: September 2000  
1234567...47

中文翻译

下载PDF

与M5LV-128/104-12AI相关器件

型号 品牌 获取价格 描述 数据表
M5LV-128/104-12HC LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-12HI LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-12VC LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-12VI LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-12VNC LATTICE

获取价格

 		EE PLD, 12ns, CMOS, PQFP144, TQFP-144
M5LV-128/104-12YC LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-12YI LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-15AC LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-15AI LATTICE

获取价格

 		Fifth Generation MACH Architecture
M5LV-128/104-15HC LATTICE

获取价格

 		Fifth Generation MACH Architecture

与M5LV-128/104-12AI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证