Datasheet > M59DR032B100N1T

M59DR032B100N1T

更新时间： 2024-11-13 20:46:07

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M59DR032B100N1T 数据手册

M59DR032A

M59DR032B

32 Mbit (2Mb x16, Dual Bank, Page) Low Voltage Flash Memory

PRELIMINARY DATA

■ SUPPLY VOLTAGE

– V

= V

= 1.65V to 2.2V: for Program,

DDQ

Erase and Read

– V

= 12V: optional Supply Voltage for fast

Program and Erase

■ ASYNCHRONOUS PAGE MODE READ

– Page Width: 4 words

BGA

– Page Access: 35ns

– Random Access: 100ns

TSOP48 (N)

12 x 20mm

FBGA48 (ZB)

8 x 6 solder balls

■ PROGRAMMING TIME

– 10µs by Word typical

– Double Word Programming Option

■ MEMORY BLOCKS

– Dual Bank Memory Array: 4 Mbit - 28 Mbit

– Parameter Blocks (Top or Bottom location)

– Main Blocks

Figure 1. Logic Diagram

■ DUAL BANK OPERATIONS

– Read within one Bank while Program or

Erase within the other

DD DDQ PP

– No delay between Read and Write operations

■ BLOCK PROTECTION/UNPROTECTION

– All Blocks protected at Power Up

A0-A20

DQ0-DQ15

– Any combination of Blocks can be protected

– WP for Block Locking

M59DR032A

M59DR032B

■ COMMON FLASH INTERFACE (CFI)

■ 64 bit SECURITY CODE

■ ERASE SUSPEND and RESUME MODES

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

AI02544B

– Device Code, M59DR032A: A0h

– Device Code, M59DR032B: A1h

October 1999

1/38

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

12 3 4 5 6 7...38

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