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M54HCT368F1R PDF预览

M54HCT368F1R

更新时间: 2024-11-01 22:19:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
11页 250K
描述
HEX BUS BUFFER 3-STATE HCT367 NONINVERTING, HCT368 INVERTING

M54HCT368F1R 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
其他特性:ONE FUNCTION WITH TWO BITS控制类型:ENABLE LOW
系列:HCTJESD-30 代码:R-GDIP-T16
JESD-609代码:e0负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:6功能数量:1
端口数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:36 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

M54HCT368F1R 数据手册

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M54/M74HCT367  
M54/M74HCT368  
HEX BUS BUFFER (3-STATE)  
HCT367 NON INVERTING, HCT368 INVERTING  
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HIGH SPEED  
tPD = 11 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE WITH  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
54/74LS367/368  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXM1R  
M74HCTXXXB1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT367 and the M54/74HCT368 are  
high speed CMOS HEX BUS BUFFER (3-STATE)  
fabricated in silicon gate C2MOS technology. They  
have the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
These devices contain six buffers, four buffers are  
controlled by an enable input (G1) and the other two  
buffers are controlled by the other enable input  
(G2) ; the outputs of each buffer group are enabled  
when G1 and/or G2 inputs are held low, and  
when held high these outputs are disabled to be  
high-impedance.  
PIN CONNECTIONS (top view)  
HCT368  
Theseoutputs are capable of driving upto15LSTTL  
loads. The designer has a choice of non-inverting  
outputs (HCT367) and inverting outputs (HCT368).  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
HCT367  
This integrated circuit has input and output charac-  
teristics that are fully compatible with 54/74 LSTTL  
logic families. M54/74HCT devices are designed to  
directly interface HSC2MOS systems with TTL and  
NMOS components. They are also plug in replace-  
ments for LSTTL devices giving a reduction of  
power consumption.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
February 1993  
1/11  

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