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M54HC191DG PDF预览

M54HC191DG

更新时间: 2024-10-02 17:33:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
9页 235K
描述
抗辐照4位同步二进制递增/递减计数器

M54HC191DG 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.84逻辑集成电路类型:BINARY COUNTER

M54HC191DG 数据手册

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M54HC10  
M74HC10  
TRIPLE 3-INPUT NAND GATE  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 6 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS10  
ORDER CODES :  
M54HC10F1R  
M74HC10B1R  
M74HC10M1R  
M74HC10C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC10 is a high speed CMOS TRIPLE  
3-INPUT NAND GATE fabricated with silicon gate  
C2MOS technology.  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
The internal circuit is composed of 3 stages includ-  
ing buffer output, which enables high noise im-  
munity and stable output.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/9  

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