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M54HC02KG PDF预览

M54HC02KG

更新时间: 2024-11-05 17:33:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
9页 235K
描述
抗辐照四路2输入或非门

M54HC02KG 技术参数

生命周期:Active包装说明:DFP, FL14,.2
Reach Compliance Code:compliant风险等级:5.7
其他特性:SEATED HT-CALCULATED系列:HC/UH
JESD-30 代码:R-CDFP-F14长度:9.95 mm
逻辑集成电路类型:NOR GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DFP
封装等效代码:FL14,.2封装形状:RECTANGULAR
封装形式:FLATPACK包装方法:STRIP PACK
施密特触发器:NO座面最大高度:2.33 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
总剂量:50k Rad(Si) V宽度:6.91 mm
Base Number Matches:1

M54HC02KG 数据手册

 浏览型号M54HC02KG的Datasheet PDF文件第2页浏览型号M54HC02KG的Datasheet PDF文件第3页浏览型号M54HC02KG的Datasheet PDF文件第4页浏览型号M54HC02KG的Datasheet PDF文件第5页浏览型号M54HC02KG的Datasheet PDF文件第6页浏览型号M54HC02KG的Datasheet PDF文件第7页 
M54HC10  
M74HC10  
TRIPLE 3-INPUT NAND GATE  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 6 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS10  
ORDER CODES :  
M54HC10F1R  
M74HC10B1R  
M74HC10M1R  
M74HC10C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC10 is a high speed CMOS TRIPLE  
3-INPUT NAND GATE fabricated with silicon gate  
C2MOS technology.  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
The internal circuit is composed of 3 stages includ-  
ing buffer output, which enables high noise im-  
munity and stable output.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/9  

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